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Commit cc75b92d authored by Thomas Gleixner's avatar Thomas Gleixner Committed by Linus Torvalds
Browse files

genirq: mark io_apic level interrupts to avoid resend 



Level type interrupts do not need to be resent.  It was also found that
some chipsets get confused in case of the resend.

Mark the ioapic level type interrupts as such to avoid the resend
functionality in the generic irq code.

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 2464286a

arch/i386/kernel/io_apic.c

+5 −2
Original line number Diff line number Diff line
@@ -1256,12 +1256,15 @@ static struct irq_chip ioapic_chip; 
static void ioapic_register_intr(int irq, int vector, unsigned long trigger)

{

	if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||

			trigger == IOAPIC_LEVEL)

	    trigger == IOAPIC_LEVEL) {

		irq_desc[irq].status |= IRQ_LEVEL;

		set_irq_chip_and_handler_name(irq, &ioapic_chip,

					 handle_fasteoi_irq, "fasteoi");

	else

	} else {

		irq_desc[irq].status &= ~IRQ_LEVEL;

		set_irq_chip_and_handler_name(irq, &ioapic_chip,

					 handle_edge_irq, "edge");

	}

	set_intr_gate(vector, interrupt[irq]);

}

arch/x86_64/kernel/io_apic.c

+5 −2
Original line number Diff line number Diff line
@@ -800,13 +800,16 @@ static struct irq_chip ioapic_chip; 


static void ioapic_register_intr(int irq, unsigned long trigger)

{

	if (trigger)

	if (trigger) {

		irq_desc[irq].status |= IRQ_LEVEL;

		set_irq_chip_and_handler_name(irq, &ioapic_chip,

					      handle_fasteoi_irq, "fasteoi");

	else

	} else {

		irq_desc[irq].status &= ~IRQ_LEVEL;

		set_irq_chip_and_handler_name(irq, &ioapic_chip,

					      handle_edge_irq, "edge");

	}

}



static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,

			      int trigger, int polarity)