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Commit cc0f6398 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915: PIPE_CONTROL_TLB_INVALIDATE 



This has showed up in several other patches. It's required for the next
context workaround.

I tested this one on its own and saw no differences in basic tests
(performance or otherwise). This patch is relatively likely to cause
regressions, hence why it's split out.

Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
parent e37ec39b

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -294,6 +294,7 @@ 
#define   DISPLAY_PLANE_B           (1<<20)

#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))

#define   PIPE_CONTROL_CS_STALL				(1<<20)

#define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)

#define   PIPE_CONTROL_QW_WRITE				(1<<14)

#define   PIPE_CONTROL_DEPTH_STALL			(1<<13)

#define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)

drivers/gpu/drm/i915/intel_ringbuffer.c

+1 −0
Original line number Diff line number Diff line
@@ -226,6 +226,7 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring, 
	 * impact.

	 */

	flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;

	flags |= PIPE_CONTROL_TLB_INVALIDATE;

	flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;

	flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;

	flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;