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Commit cb54cb66 authored by Jordan Crouse's avatar Jordan Crouse Committed by Sushmita Susheelendra
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msm: kgsl: Simplify snapshot register dumping 



Back when we were younger and less wise the snapshot format forced us
to squeeze all of the registers into one section.  Later we realized
that was entirely silly - there is no reason why we shouldn't be able
to have multiple register sections.  Unfortunately the old
infrastucture remains until this very moment when we rip it out and
greatly simplify how register dumping works and get rid of a few
functions and structs in the process.

Change-Id: Ic0dedbad2ef14a580122e918832f322d88221592
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent 494ca1d5

drivers/gpu/msm/adreno.c

+3 −2
Original line number Diff line number Diff line
@@ -1299,6 +1299,9 @@ static int adreno_init(struct kgsl_device *device) 
	else if ((adreno_is_a405(adreno_dev)) || (adreno_is_a420(adreno_dev)))

		adreno_a4xx_pwron_fixup_init(adreno_dev);



	if (gpudev->init != NULL)

		gpudev->init(adreno_dev);



	set_bit(ADRENO_DEVICE_INITIALIZED, &adreno_dev->priv);



	/* Use shader offset and length defined in gpudev */
@@ -1361,8 +1364,6 @@ static int adreno_init(struct kgsl_device *device) 
			WARN(1, "adreno: GPU preemption is disabled\n");

	}



	if (gpudev->cp_crash_dumper_init)

		gpudev->cp_crash_dumper_init(adreno_dev);

	return 0;

}

drivers/gpu/msm/adreno.h

+8 −11
Original line number Diff line number Diff line
@@ -362,10 +362,6 @@ struct adreno_device { 
	uint32_t lm_threshold_count;

	uint32_t lm_threshold_cross;



	struct kgsl_memdesc capturescript;

	struct kgsl_memdesc snapshot_registers;

	bool capturescript_working;



	unsigned int speed_bin;

	unsigned int quirks;

};
@@ -506,6 +502,7 @@ enum adreno_regs { 
	ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_SIZE,

	ADRENO_REG_VBIF_XIN_HALT_CTRL0,

	ADRENO_REG_VBIF_XIN_HALT_CTRL1,

	ADRENO_REG_VBIF_VERSION,

	ADRENO_REG_REGISTER_MAX,

};
@@ -549,14 +546,14 @@ struct adreno_vbif_platform { 
/*

 * struct adreno_vbif_snapshot_registers - Holds an array of vbif registers

 * listed for snapshot dump for a particular core

 * @vbif_version: vbif version

 * @vbif_snapshot_registers: vbif registers listed for snapshot dump

 * @vbif_snapshot_registers_count: count of vbif registers listed for snapshot

 * @version: vbif version

 * @registers: vbif registers listed for snapshot dump

 * @count: count of vbif registers listed for snapshot

 */

struct adreno_vbif_snapshot_registers {

	const unsigned int vbif_version;

	const unsigned int *vbif_snapshot_registers;

	const int vbif_snapshot_registers_count;

	const unsigned int version;

	const unsigned int *registers;

	const int count;

};



/**
@@ -677,6 +674,7 @@ struct adreno_gpudev { 
	void (*irq_trace)(struct adreno_device *, unsigned int status);

	void (*snapshot)(struct adreno_device *, struct kgsl_snapshot *);

	void (*platform_setup)(struct adreno_device *);

	void (*init)(struct adreno_device *);

	int (*rb_init)(struct adreno_device *, struct adreno_ringbuffer *);

	int (*hw_init)(struct adreno_device *);

	int (*switch_to_unsecure_mode)(struct adreno_device *,
@@ -705,7 +703,6 @@ struct adreno_gpudev { 
	int (*preemption_init)(struct adreno_device *);

	void (*preemption_schedule)(struct adreno_device *);

	void (*enable_64bit)(struct adreno_device *);

	void (*cp_crash_dumper_init)(struct adreno_device *);

};



struct log_field {

drivers/gpu/msm/adreno_a3xx_snapshot.c

+9 −38
Original line number Diff line number Diff line
@@ -65,8 +65,6 @@ static const unsigned int a3xx_registers[] = { 
	0x303C, 0x303C, 0x305E, 0x305F,

};



static const unsigned int a3xx_registers_count = ARRAY_SIZE(a3xx_registers) / 2;



/* Removed the following HLSQ register ranges from being read during

 * fault tolerance since reading the registers may cause the device to hang:

 */
@@ -76,17 +74,12 @@ static const unsigned int a3xx_hlsq_registers[] = { 
	0x2600, 0x2612, 0x2614, 0x2617, 0x261a, 0x261a,

};



static const unsigned int a3xx_hlsq_registers_count =

			ARRAY_SIZE(a3xx_hlsq_registers) / 2;



/* The set of additional registers to be dumped for A330 */



static const unsigned int a330_registers[] = {

	0x1d0, 0x1d0, 0x1d4, 0x1d4, 0x453, 0x453,

};



static const unsigned int a330_registers_count = ARRAY_SIZE(a330_registers) / 2;



/* Shader memory size in words */

#define SHADER_MEMORY_SIZE 0x4000
@@ -236,11 +229,10 @@ static void a3xx_snapshot_debugbus(struct kgsl_device *device, 
	}

}



static void _snapshot_hlsq_regs(struct kgsl_snapshot_registers *regs,

	struct kgsl_snapshot_registers_list *list,

	struct adreno_device *adreno_dev)

static void _snapshot_hlsq_regs(struct kgsl_device *device,

		struct kgsl_snapshot *snapshot)

{

	struct kgsl_device *device = &adreno_dev->dev;

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);



	/*

	 * Trying to read HLSQ registers when the HLSQ block is busy
@@ -289,19 +281,7 @@ static void _snapshot_hlsq_regs(struct kgsl_snapshot_registers *regs, 
			return;

	}



	regs[list->count].regs = (unsigned int *) a3xx_hlsq_registers;

	regs[list->count].count = a3xx_hlsq_registers_count;

	list->count++;

}



static void _snapshot_a330_regs(struct kgsl_snapshot_registers *regs,

	struct kgsl_snapshot_registers_list *list)

{

	/* For A330, append the additional list of new registers to grab */

	regs[list->count].regs = (unsigned int *) a330_registers;

	regs[list->count].count = a330_registers_count;

	regs[list->count].dump = 1;

	list->count++;

	SNAPSHOT_REGISTERS(device, snapshot, a3xx_hlsq_registers);

}



/*
@@ -318,27 +298,18 @@ void a3xx_snapshot(struct adreno_device *adreno_dev, 
{

	struct kgsl_device *device = &adreno_dev->dev;

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	struct kgsl_snapshot_registers_list list;

	struct kgsl_snapshot_registers regs[5];

	struct adreno_snapshot_data *snap_data = gpudev->snapshot_data;

	unsigned int reg;



	list.registers = regs;

	list.count = 0;



	/* Disable Clock gating temporarily for the debug bus to work */

	adreno_writereg(adreno_dev, ADRENO_REG_RBBM_CLOCK_CTL, 0x00);



	/* Store relevant registers in list to snapshot */

	adreno_snapshot_regs(regs, &list, a3xx_registers,

			a3xx_registers_count, 1);

	_snapshot_hlsq_regs(regs, &list, adreno_dev);

	if (adreno_is_a330(adreno_dev) || adreno_is_a305b(adreno_dev))

		_snapshot_a330_regs(regs, &list);

	SNAPSHOT_REGISTERS(device, snapshot, a3xx_registers);



	_snapshot_hlsq_regs(device, snapshot);



	/* Master set of (non debug) registers */

	kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS,

		snapshot, kgsl_snapshot_dump_regs, &list);

	if (adreno_is_a330(adreno_dev) || adreno_is_a305b(adreno_dev))

		SNAPSHOT_REGISTERS(device, snapshot, a330_registers);



	kgsl_snapshot_indexed_registers(device, snapshot,

		A3XX_CP_STATE_DEBUG_INDEX, A3XX_CP_STATE_DEBUG_DATA,

drivers/gpu/msm/adreno_a4xx.c

+2 −0
Original line number Diff line number Diff line
@@ -910,6 +910,8 @@ static unsigned int a4xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
				A4XX_VBIF_XIN_HALT_CTRL0),

	ADRENO_REG_DEFINE(ADRENO_REG_VBIF_XIN_HALT_CTRL1,

				A4XX_VBIF_XIN_HALT_CTRL1),

	ADRENO_REG_DEFINE(ADRENO_REG_VBIF_VERSION,

				A4XX_VBIF_VERSION),

};



static const struct adreno_reg_offsets a4xx_reg_offsets = {

drivers/gpu/msm/adreno_a4xx_snapshot.c

+15 −66
Original line number Diff line number Diff line
@@ -61,8 +61,6 @@ static const unsigned int a4xx_registers[] = { 
	0x2600, 0x2604, 0x2608, 0x26A9,

};



static const unsigned int a4xx_registers_count = ARRAY_SIZE(a4xx_registers) / 2;



static const unsigned int a4xx_sp_tp_registers[] = {

	/* SP */

	0x0EC0, 0x0ECF,
@@ -80,9 +78,6 @@ static const unsigned int a4xx_sp_tp_registers[] = { 
	0x2780, 0x2782, 0x2784, 0x278F, 0x27A0, 0x27A6,

};



static const unsigned int a4xx_sp_tp_registers_count =

			ARRAY_SIZE(a4xx_sp_tp_registers) / 2;



static const unsigned int a4xx_ppd_registers[] = {

	/* V2 Thresholds */

	0x01B2, 0x01B5,
@@ -90,9 +85,6 @@ static const unsigned int a4xx_ppd_registers[] = { 
	0x01B9, 0x01BE,

};



static const unsigned int a4xx_ppd_registers_count =

			ARRAY_SIZE(a4xx_ppd_registers) / 2;



static const unsigned int a4xx_xpu_registers[] = {

	/* XPU */

	0x2C00, 0x2C01, 0x2C10, 0x2C10, 0x2C12, 0x2C16, 0x2C1D, 0x2C20,
@@ -100,9 +92,6 @@ static const unsigned int a4xx_xpu_registers[] = { 
	0x2C50, 0x2C50, 0x2C52, 0x2C56, 0x2C80, 0x2C80, 0x2C94, 0x2C95,

};



static const unsigned int a4xx_xpu_reg_cnt =

				ARRAY_SIZE(a4xx_xpu_registers)/2;



static const unsigned int a4xx_vbif_ver_20000000_registers[] = {

	/* VBIF version 0x20000000 & IOMMU V1 */

	0x3000, 0x3007, 0x300C, 0x3014, 0x3018, 0x301D, 0x3020, 0x3022,
@@ -191,9 +180,6 @@ static const struct adreno_vbif_snapshot_registers 
				ARRAY_SIZE(a4xx_vbif_ver_20050000_registers)/2},

};



static const unsigned int a4xx_vbif_snapshot_reg_cnt =

				ARRAY_SIZE(a4xx_vbif_snapshot_registers);



#define A4XX_NUM_SHADER_BANKS 4

#define A405_NUM_SHADER_BANKS 1

/* Shader memory size in words */
@@ -519,31 +505,6 @@ static void a4xx_reset_hlsq(struct kgsl_device *device) 
	kgsl_regwrite(device, A4XX_HLSQ_TIMEOUT_THRESHOLD, val);

}



static void a4xx_snapshot_vbif_registers(struct kgsl_device *device,

				struct kgsl_snapshot_registers *regs,

				struct kgsl_snapshot_registers_list *list)

{

	unsigned int vbif_version = 0;

	int i;

	int found = 0;



	kgsl_regread(device, A4XX_VBIF_VERSION, &vbif_version);



	for (i = 0; i < a4xx_vbif_snapshot_reg_cnt; i++) {

		if (vbif_version ==

			a4xx_vbif_snapshot_registers[i].vbif_version) {

			found = 1;

			break;

		}

	}

	if (found)

		adreno_snapshot_regs(regs, list,

				a4xx_vbif_snapshot_registers[i].

					vbif_snapshot_registers,

				a4xx_vbif_snapshot_registers[i].

					vbif_snapshot_registers_count, 1);

}



/*

 * a4xx_snapshot() - A4XX GPU snapshot function

 * @adreno_dev: Device being snapshotted
@@ -557,13 +518,8 @@ void a4xx_snapshot(struct adreno_device *adreno_dev, 
{

	struct kgsl_device *device = &adreno_dev->dev;

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	struct kgsl_snapshot_registers_list list;

	struct kgsl_snapshot_registers regs[5];

	struct adreno_snapshot_data *snap_data = gpudev->snapshot_data;



	list.registers = regs;

	list.count = 0;



	/* Disable SP clock gating for the debug bus to work */

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_SP0, 0);

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_SP1, 0);
@@ -578,32 +534,25 @@ void a4xx_snapshot(struct adreno_device *adreno_dev, 
	kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL, 0);

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2, 0);



	/* Store relevant registers in list to snapshot */

	adreno_snapshot_regs(regs, &list, a4xx_registers,

			a4xx_registers_count, 1);

	/* Turn on MMU clocks since we read MMU registers */

	kgsl_mmu_enable_clk(&device->mmu);



	adreno_snapshot_regs(regs, &list, a4xx_sp_tp_registers,

			a4xx_sp_tp_registers_count,

			(adreno_is_a430(adreno_dev) ? 1 : 0));

	/* Master set of (non debug) registers */



	if (adreno_is_a420(adreno_dev)) {

		adreno_snapshot_regs(regs, &list, a4xx_xpu_registers,

				a4xx_xpu_reg_cnt, 1);

	}

	SNAPSHOT_REGISTERS(device, snapshot, a4xx_registers);



	if (adreno_is_a430v2(adreno_dev)) {

		adreno_snapshot_regs(regs, &list, a4xx_ppd_registers,

				a4xx_ppd_registers_count, 1);

	}

	if (adreno_is_a430(adreno_dev))

		SNAPSHOT_REGISTERS(device, snapshot, a4xx_sp_tp_registers);



	a4xx_snapshot_vbif_registers(device, regs, &list);

	if (adreno_is_a420(adreno_dev))

		SNAPSHOT_REGISTERS(device, snapshot, a4xx_xpu_registers);



	/* Turn on MMU clocks since we read MMU registers */

	kgsl_mmu_enable_clk(&device->mmu);

	if (adreno_is_a430v2(adreno_dev))

		SNAPSHOT_REGISTERS(device, snapshot, a4xx_ppd_registers);



	/* Master set of (non debug) registers */

	kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS, snapshot,

		kgsl_snapshot_dump_regs, &list);

	adreno_snapshot_vbif_registers(device, snapshot,

		a4xx_vbif_snapshot_registers,

		ARRAY_SIZE(a4xx_vbif_snapshot_registers));



	kgsl_mmu_disable_clk(&device->mmu);
@@ -646,9 +595,9 @@ void a4xx_snapshot(struct adreno_device *adreno_dev, 


	if (!adreno_is_a430(adreno_dev)) {

		a4xx_reset_hlsq(device);



		kgsl_snapshot_dump_skipped_regs(device, &list);

		SNAPSHOT_REGISTERS(device, snapshot, a4xx_sp_tp_registers);

	}



	/* Shader working/shadow memory */

	kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG,

		snapshot, a4xx_snapshot_shader_memory,