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Commit cad2a2d7 authored by Eugeni Dodonov's avatar Eugeni Dodonov Committed by Daniel Vetter
Browse files

drm/i915: introduce haswell_init_clock_gating 



This is based on Ivy Bridge clock gating for now, but is subject to
changes in the future.

Note: Compared to the ivb clock gating this drops the the IDICOS
medium uncore sharing tuned in

commit 20848223
Author: Ben Widawsky <ben@bwidawsk.net>
Date:   Fri May 4 18:58:59 2012 -0700

    drm/i915: set IDICOS to medium uncore resources

Eugeni wants to benchmark the effect of this first.

Signed-off-by: default avatarEugeni Dodonov <eugeni.dodonov@intel.com>
[danvet: added note]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 88509484

drivers/gpu/drm/i915/intel_pm.c

+53 −1
Original line number Diff line number Diff line
@@ -3417,6 +3417,58 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) 
	I915_WRITE(GEN7_FF_THREAD_MODE, reg);

}



static void haswell_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int pipe;

	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;



	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);



	I915_WRITE(WM3_LP_ILK, 0);

	I915_WRITE(WM2_LP_ILK, 0);

	I915_WRITE(WM1_LP_ILK, 0);



	/* According to the spec, bit 13 (RCZUNIT) must be set on IVB.

	 * This implements the WaDisableRCZUnitClockGating workaround.

	 */

	I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);



	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);



	I915_WRITE(IVB_CHICKEN3,

		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |

		   CHICKEN3_DGMG_DONE_FIX_DISABLE);



	/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */

	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,

		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);



	/* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */

	I915_WRITE(GEN7_L3CNTLREG1,

			GEN7_WA_FOR_GEN7_L3_CONTROL);

	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,

			GEN7_WA_L3_CHICKEN_MODE);



	/* This is required by WaCatErrorRejectionIssue */

	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,

			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |

			GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);



	for_each_pipe(pipe) {

		I915_WRITE(DSPCNTR(pipe),

			   I915_READ(DSPCNTR(pipe)) |

			   DISPPLANE_TRICKLE_FEED_DISABLE);

		intel_flush_display_plane(dev_priv, pipe);

	}



	gen7_setup_fixed_func_scheduler(dev_priv);



	/* WaDisable4x2SubspanOptimization */

	I915_WRITE(CACHE_MODE_1,

		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));

}



static void ivybridge_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3826,7 +3878,7 @@ void intel_init_pm(struct drm_device *dev) 
					      "Disable CxSR\n");

				dev_priv->display.update_wm = NULL;

			}

			dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;

			dev_priv->display.init_clock_gating = haswell_init_clock_gating;

			dev_priv->display.sanitize_pm = gen6_sanitize_pm;

		} else

			dev_priv->display.update_wm = NULL;