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Commit cabaf3ed authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'next/irq-s3c24xx' of... 

Merge branch 'next/irq-s3c24xx' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers

From Kukjin Kim <kgene.kim@samsung.com>:

Here is finish the irq rework for s3c2412, s3c2440 and s3c2442 into the new
structure and eint0 to 3 on the s3c2412.

* 'next/irq-s3c24xx' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung

:
  gpio: samsung: fixes build warning with s3c2410_defconfig
  ARM: S3C24XX: handle s3c2412 eints using new infrastructure
  ARM: S3C24XX: add soc_is_s3c2412 option
  ARM: S3C24XX: include first 4 bits of the eint register in irq mapping
  ARM: S3C24XX: transform s3c2412 irqs into new structure
  ARM: S3C24XX: modify s3c2412 irq init to initialize all irqs
  ARM: S3C24XX: move s3c2412 irq init to common code
  ARM: S3C24XX: use samsung_sync_wakemask in s3c2412 pm
  ARM: S3C24XX: transform s3c2440 irqs into new structure
  ARM: S3C24XX: transform s3c2442 irqs into new structure
  ARM: S3C24XX: integrate s3c2440 irqs into common init
  ARM: S3C24XX: move s3c2440 irqs to common irq code
  ARM: S3C24XX: create dedicated irq init functions for s3c2440 and s3c2442
  ARM: S3C24XX: move s3c244x irq init to common irq code

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents bffc5ce3 d97fedef

arch/arm/mach-s3c24xx/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -407,6 +407,7 @@ config S3C2412_DMA 
config S3C2412_PM

	bool

	select S3C2412_PM_SLEEP

	select SAMSUNG_WAKEMASK

	help

	  Internal config node to apply S3C2412 power management

arch/arm/mach-s3c24xx/Makefile

+3 −3
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ obj-$(CONFIG_S3C2410_DMA) += dma-s3c2410.o 
obj-$(CONFIG_S3C2410_PLL)	+= pll-s3c2410.o

obj-$(CONFIG_S3C2410_PM)	+= pm-s3c2410.o sleep-s3c2410.o



obj-$(CONFIG_CPU_S3C2412)	+= s3c2412.o irq-s3c2412.o clock-s3c2412.o

obj-$(CONFIG_CPU_S3C2412)	+= s3c2412.o clock-s3c2412.o

obj-$(CONFIG_S3C2412_CPUFREQ)	+= cpufreq-s3c2412.o

obj-$(CONFIG_S3C2412_DMA)	+= dma-s3c2412.o

obj-$(CONFIG_S3C2412_PM)	+= pm-s3c2412.o
@@ -31,9 +31,9 @@ obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o 
obj-$(CONFIG_CPU_S3C2416)	+= s3c2416.o clock-s3c2416.o

obj-$(CONFIG_S3C2416_PM)	+= pm-s3c2416.o



obj-$(CONFIG_CPU_S3C2440)	+= s3c2440.o irq-s3c2440.o clock-s3c2440.o

obj-$(CONFIG_CPU_S3C2440)	+= s3c2440.o clock-s3c2440.o

obj-$(CONFIG_CPU_S3C2442)	+= s3c2442.o

obj-$(CONFIG_CPU_S3C244X)	+= s3c244x.o irq-s3c244x.o clock-s3c244x.o

obj-$(CONFIG_CPU_S3C244X)	+= s3c244x.o clock-s3c244x.o

obj-$(CONFIG_S3C2440_CPUFREQ)	+= cpufreq-s3c2440.o

obj-$(CONFIG_S3C2440_DMA)	+= dma-s3c2440.o

obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o

arch/arm/mach-s3c24xx/common.h

+3 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no); 
extern void s3c2412_init_clocks(int xtal);

extern  int s3c2412_baseclk_add(void);

extern void s3c2412_restart(char mode, const char *cmd);

extern void s3c2412_init_irq(void);

#else

#define s3c2412_init_clocks NULL

#define s3c2412_init_uarts NULL
@@ -73,6 +74,7 @@ extern void s3c244x_restart(char mode, const char *cmd); 
#ifdef CONFIG_CPU_S3C2440

extern  int s3c2440_init(void);

extern void s3c2440_map_io(void);

extern void s3c2440_init_irq(void);

#else

#define s3c2440_init NULL

#define s3c2440_map_io NULL
@@ -81,6 +83,7 @@ extern void s3c2440_map_io(void); 
#ifdef CONFIG_CPU_S3C2442

extern  int s3c2442_init(void);

extern void s3c2442_map_io(void);

extern void s3c2442_init_irq(void);

#else

#define s3c2442_init NULL

#define s3c2442_map_io NULL

arch/arm/mach-s3c24xx/include/mach/irqs.h

+31 −27
Original line number Diff line number Diff line
@@ -59,49 +59,53 @@ 
#define IRQ_ADCPARENT  S3C2410_IRQ(31)



/* interrupts generated from the external interrupts sources */

#define IRQ_EINT4      S3C2410_IRQ(32)	   /* 48 */

#define IRQ_EINT5      S3C2410_IRQ(33)

#define IRQ_EINT6      S3C2410_IRQ(34)

#define IRQ_EINT7      S3C2410_IRQ(35)

#define IRQ_EINT8      S3C2410_IRQ(36)

#define IRQ_EINT9      S3C2410_IRQ(37)

#define IRQ_EINT10     S3C2410_IRQ(38)

#define IRQ_EINT11     S3C2410_IRQ(39)

#define IRQ_EINT12     S3C2410_IRQ(40)

#define IRQ_EINT13     S3C2410_IRQ(41)

#define IRQ_EINT14     S3C2410_IRQ(42)

#define IRQ_EINT15     S3C2410_IRQ(43)

#define IRQ_EINT16     S3C2410_IRQ(44)

#define IRQ_EINT17     S3C2410_IRQ(45)

#define IRQ_EINT18     S3C2410_IRQ(46)

#define IRQ_EINT19     S3C2410_IRQ(47)

#define IRQ_EINT20     S3C2410_IRQ(48)	   /* 64 */

#define IRQ_EINT21     S3C2410_IRQ(49)

#define IRQ_EINT22     S3C2410_IRQ(50)

#define IRQ_EINT23     S3C2410_IRQ(51)

#define IRQ_EINT0_2412 S3C2410_IRQ(32)

#define IRQ_EINT1_2412 S3C2410_IRQ(33)

#define IRQ_EINT2_2412 S3C2410_IRQ(34)

#define IRQ_EINT3_2412 S3C2410_IRQ(35)

#define IRQ_EINT4      S3C2410_IRQ(36)	   /* 52 */

#define IRQ_EINT5      S3C2410_IRQ(37)

#define IRQ_EINT6      S3C2410_IRQ(38)

#define IRQ_EINT7      S3C2410_IRQ(39)

#define IRQ_EINT8      S3C2410_IRQ(40)

#define IRQ_EINT9      S3C2410_IRQ(41)

#define IRQ_EINT10     S3C2410_IRQ(42)

#define IRQ_EINT11     S3C2410_IRQ(43)

#define IRQ_EINT12     S3C2410_IRQ(44)

#define IRQ_EINT13     S3C2410_IRQ(45)

#define IRQ_EINT14     S3C2410_IRQ(46)

#define IRQ_EINT15     S3C2410_IRQ(47)

#define IRQ_EINT16     S3C2410_IRQ(48)

#define IRQ_EINT17     S3C2410_IRQ(49)

#define IRQ_EINT18     S3C2410_IRQ(50)

#define IRQ_EINT19     S3C2410_IRQ(51)

#define IRQ_EINT20     S3C2410_IRQ(52)	   /* 68 */

#define IRQ_EINT21     S3C2410_IRQ(53)

#define IRQ_EINT22     S3C2410_IRQ(54)

#define IRQ_EINT23     S3C2410_IRQ(55)



#define IRQ_EINT_BIT(x)	((x) - IRQ_EINT4 + 4)

#define IRQ_EINT(x)    (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))



#define IRQ_LCD_FIFO   S3C2410_IRQ(52)

#define IRQ_LCD_FRAME  S3C2410_IRQ(53)

#define IRQ_LCD_FIFO   S3C2410_IRQ(56)

#define IRQ_LCD_FRAME  S3C2410_IRQ(57)



/* IRQs for the interal UARTs, and ADC

 * these need to be ordered in number of appearance in the

 * SUBSRC mask register

*/



#define S3C2410_IRQSUB(x)	S3C2410_IRQ((x)+54)

#define S3C2410_IRQSUB(x)	S3C2410_IRQ((x)+58)



#define IRQ_S3CUART_RX0		S3C2410_IRQSUB(0)	/* 70 */

#define IRQ_S3CUART_RX0		S3C2410_IRQSUB(0)	/* 74 */

#define IRQ_S3CUART_TX0		S3C2410_IRQSUB(1)

#define IRQ_S3CUART_ERR0	S3C2410_IRQSUB(2)



#define IRQ_S3CUART_RX1		S3C2410_IRQSUB(3)	/* 73 */

#define IRQ_S3CUART_RX1		S3C2410_IRQSUB(3)	/* 77 */

#define IRQ_S3CUART_TX1		S3C2410_IRQSUB(4)

#define IRQ_S3CUART_ERR1	S3C2410_IRQSUB(5)



#define IRQ_S3CUART_RX2		S3C2410_IRQSUB(6)	/* 76 */

#define IRQ_S3CUART_RX2		S3C2410_IRQSUB(6)	/* 80 */

#define IRQ_S3CUART_TX2		S3C2410_IRQSUB(7)

#define IRQ_S3CUART_ERR2	S3C2410_IRQSUB(8)
@@ -136,7 +140,7 @@ 


/* second interrupt-register of s3c2416/s3c2450 */



#define S3C2416_IRQ(x)		S3C2410_IRQ((x) + 54 + 29)

#define S3C2416_IRQ(x)		S3C2410_IRQ((x) + 58 + 29)

#define IRQ_S3C2416_2D		S3C2416_IRQ(0)

#define IRQ_S3C2416_IIC1	S3C2416_IRQ(1)

#define IRQ_S3C2416_RESERVED2	S3C2416_IRQ(2)

arch/arm/mach-s3c24xx/irq-s3c2412.c

deleted100644 → 0
+0 −215
Original line number Diff line number Diff line 
/* linux/arch/arm/mach-s3c2412/irq.c

 *

 * Copyright (c) 2006 Simtec Electronics

 *	Ben Dooks <ben@simtec.co.uk>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 *

*/



#include <linux/init.h>

#include <linux/module.h>

#include <linux/interrupt.h>

#include <linux/ioport.h>

#include <linux/device.h>

#include <linux/io.h>



#include <mach/hardware.h>

#include <asm/irq.h>



#include <asm/mach/irq.h>



#include <mach/regs-irq.h>

#include <mach/regs-gpio.h>



#include <plat/cpu.h>

#include <plat/irq.h>

#include <plat/pm.h>



#include "s3c2412-power.h"



#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)

#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))



/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by

 * having them turn up in both the INT* and the EINT* registers. Whilst

 * both show the status, they both now need to be acked when the IRQs

 * go off.

*/



static void

s3c2412_irq_mask(struct irq_data *data)

{

	unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);

	unsigned long mask;



	mask = __raw_readl(S3C2410_INTMSK);

	__raw_writel(mask | bitval, S3C2410_INTMSK);



	mask = __raw_readl(S3C2412_EINTMASK);

	__raw_writel(mask | bitval, S3C2412_EINTMASK);

}



static inline void

s3c2412_irq_ack(struct irq_data *data)

{

	unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);



	__raw_writel(bitval, S3C2412_EINTPEND);

	__raw_writel(bitval, S3C2410_SRCPND);

	__raw_writel(bitval, S3C2410_INTPND);

}



static inline void

s3c2412_irq_maskack(struct irq_data *data)

{

	unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);

	unsigned long mask;



	mask = __raw_readl(S3C2410_INTMSK);

	__raw_writel(mask|bitval, S3C2410_INTMSK);



	mask = __raw_readl(S3C2412_EINTMASK);

	__raw_writel(mask | bitval, S3C2412_EINTMASK);



	__raw_writel(bitval, S3C2412_EINTPEND);

	__raw_writel(bitval, S3C2410_SRCPND);

	__raw_writel(bitval, S3C2410_INTPND);

}



static void

s3c2412_irq_unmask(struct irq_data *data)

{

	unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);

	unsigned long mask;



	mask = __raw_readl(S3C2412_EINTMASK);

	__raw_writel(mask & ~bitval, S3C2412_EINTMASK);



	mask = __raw_readl(S3C2410_INTMSK);

	__raw_writel(mask & ~bitval, S3C2410_INTMSK);

}



static struct irq_chip s3c2412_irq_eint0t4 = {

	.irq_ack	= s3c2412_irq_ack,

	.irq_mask	= s3c2412_irq_mask,

	.irq_unmask	= s3c2412_irq_unmask,

	.irq_set_wake	= s3c_irq_wake,

	.irq_set_type	= s3c_irqext_type,

};



#define INTBIT(x)	(1 << ((x) - S3C2410_IRQSUB(0)))



/* CF and SDI sub interrupts */



static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc)

{

	unsigned int subsrc, submsk;



	subsrc = __raw_readl(S3C2410_SUBSRCPND);

	submsk = __raw_readl(S3C2410_INTSUBMSK);



	subsrc  &= ~submsk;



	if (subsrc & INTBIT(IRQ_S3C2412_SDI))

		generic_handle_irq(IRQ_S3C2412_SDI);



	if (subsrc & INTBIT(IRQ_S3C2412_CF))

		generic_handle_irq(IRQ_S3C2412_CF);

}



#define INTMSK_CFSDI	(1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0))

#define SUBMSK_CFSDI	INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF)



static void s3c2412_irq_cfsdi_mask(struct irq_data *data)

{

	s3c_irqsub_mask(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);

}



static void s3c2412_irq_cfsdi_unmask(struct irq_data *data)

{

	s3c_irqsub_unmask(data->irq, INTMSK_CFSDI);

}



static void s3c2412_irq_cfsdi_ack(struct irq_data *data)

{

	s3c_irqsub_maskack(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);

}



static struct irq_chip s3c2412_irq_cfsdi = {

	.name		= "s3c2412-cfsdi",

	.irq_ack	= s3c2412_irq_cfsdi_ack,

	.irq_mask	= s3c2412_irq_cfsdi_mask,

	.irq_unmask	= s3c2412_irq_cfsdi_unmask,

};



static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state)

{

	unsigned long pwrcfg;



	pwrcfg = __raw_readl(S3C2412_PWRCFG);

	if (state)

		pwrcfg &= ~S3C2412_PWRCFG_RTC_MASKIRQ;

	else

		pwrcfg |= S3C2412_PWRCFG_RTC_MASKIRQ;

	__raw_writel(pwrcfg, S3C2412_PWRCFG);



	return s3c_irq_chip.irq_set_wake(data, state);

}



static struct irq_chip s3c2412_irq_rtc_chip;



static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif)

{

	unsigned int irqno;



	for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {

		irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4,

					 handle_edge_irq);

		set_irq_flags(irqno, IRQF_VALID);

	}



	/* add demux support for CF/SDI */



	irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);



	for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {

		irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi,

					 handle_level_irq);

		set_irq_flags(irqno, IRQF_VALID);

	}



	/* change RTC IRQ's set wake method */



	s3c2412_irq_rtc_chip = s3c_irq_chip;

	s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake;



	irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);



	return 0;

}



static struct subsys_interface s3c2412_irq_interface = {

	.name		= "s3c2412_irq",

	.subsys		= &s3c2412_subsys,

	.add_dev	= s3c2412_irq_add,

};



static int s3c2412_irq_init(void)

{

	return subsys_interface_register(&s3c2412_irq_interface);

}



arch_initcall(s3c2412_irq_init);