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Commit caa48607 authored by Amir Levy's avatar Amir Levy Committed by Gerrit - the friendly Code Review server
Browse files

msm: ipa3: Adapt IPA driver to newer H/W flat file 



IPAv3 newer flat file was released in accordance to newer H/W release.
The new flat file includes update to register offsets and structure.
VPIPA release 1.5.0 is aligned to this flat file.

Change-Id: Iae5722a0894c3e96cb9829fa67cc85939d08fdf2
Signed-off-by: default avatarGhanim Fodi <gfodi@codeaurora.org>
Signed-off-by: default avatarAmir Levy <alevy@codeaurora.org>
parent b79b6ab2

drivers/platform/msm/ipa/ipa_v3/ipa.c

+1 −0
Original line number Diff line number Diff line
@@ -1139,6 +1139,7 @@ static int ipa3_setup_exception_path(void) 
	route.route_frag_def_pipe = ipa3_get_ep_mapping(

		IPA_CLIENT_APPS_LAN_CONS);

	route.route_def_hdr_table = !ipa3_ctx->hdr_tbl_lcl;

	route.route_def_retain_hdr = 1;



	if (ipa3_cfg_route(&route)) {

		IPAERR("fail to add exception hdr\n");

drivers/platform/msm/ipa/ipa_v3/ipa_i.h

+8 −0
Original line number Diff line number Diff line
@@ -469,10 +469,15 @@ struct ipa3_rt_tbl_set { 
 *	specified Status End Point. Status endpoint needs to be

 *	configured with STATUS_EN=1 Valid only for Input Pipes (IPA

 *	Consumer)

 * @status_location: Location of PKT-STATUS on destination pipe.

 *	If set to 0 (default), PKT-STATUS will be appended before the packet

 *	for this endpoint. If set to 1, PKT-STATUS will be appended after the

 *	packet for this endpoint. Valid only for Output Pipes (IPA Producer)

 */

struct ipa3_ep_cfg_status {

	bool status_en;

	u8 status_ep;

	bool status_location;

};



/**
@@ -1311,6 +1316,8 @@ struct ipa3_context { 
 * @route_frag_def_pipe: Default pipe to route fragmented exception

 *    packets and frag new rule statues, if source pipe does not have

 *    a notification status pipe defined.

 * @route_def_retain_hdr: default value of retain header. It is used

 *    when no rule was hit

 */

struct ipa3_route {

	u32 route_dis;
@@ -1318,6 +1325,7 @@ struct ipa3_route { 
	u32 route_def_hdr_table;

	u32 route_def_hdr_ofst;

	u8  route_frag_def_pipe;

	u32 route_def_retain_hdr;

};



/**

drivers/platform/msm/ipa/ipa_v3/ipa_reg.h

+18 −16
Original line number Diff line number Diff line
@@ -42,7 +42,7 @@ 
#define IPA_SHARED_MEM_SIZE_SHARED_MEM_SIZE_BMSK_v3_0  0xffff

#define IPA_SHARED_MEM_SIZE_SHARED_MEM_SIZE_SHFT_v3_0  0x0



#define IPA_ENDP_INIT_ROUTE_N_OFST_v3_0(n) (0x00000828 + 0x60 * (n))

#define IPA_ENDP_INIT_ROUTE_N_OFST_v3_0(n) (0x00000828 + 0x70 * (n))

#define IPA_ENDP_INIT_ROUTE_N_ROUTE_TABLE_INDEX_BMSK 0x1f

#define IPA_ENDP_INIT_ROUTE_N_ROUTE_TABLE_INDEX_SHFT 0x0
@@ -72,7 +72,7 @@ 
#define IPA_AGGR_FORCE_CLOSE_OFST_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK 0xFFFFF

#define IPA_AGGR_FORCE_CLOSE_OFST_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT 0



#define IPA_ENDP_INIT_AGGR_N_OFST_v3_0(n) (0x00000824 + 0x60 * (n))

#define IPA_ENDP_INIT_AGGR_N_OFST_v3_0(n) (0x00000824 + 0x70 * (n))

#define IPA_ENDP_INIT_AGGR_N_AGGR_FORCE_CLOSE_BMSK 0x1

#define IPA_ENDP_INIT_AGGR_N_AGGR_FORCE_CLOSE_SHFT 0x16

#define IPA_ENDP_INIT_AGGR_N_AGGR_PKT_LIMIT_BMSK 0x1f8000
@@ -86,7 +86,7 @@ 
#define IPA_ENDP_INIT_AGGR_N_AGGR_EN_BMSK 0x3

#define IPA_ENDP_INIT_AGGR_N_AGGR_EN_SHFT 0x0



#define IPA_ENDP_INIT_MODE_N_OFST_v3_0(n) (0x00000820 + 0x60 * (n))

#define IPA_ENDP_INIT_MODE_N_OFST_v3_0(n) (0x00000820 + 0x70 * (n))

#define IPA_ENDP_INIT_MODE_N_RMSK 0x7f

#define IPA_ENDP_INIT_MODE_N_MAX 19

#define IPA_ENDP_INIT_MODE_N_DEST_PIPE_INDEX_BMSK_v3_0 0x1f0
@@ -94,7 +94,7 @@ 
#define IPA_ENDP_INIT_MODE_N_MODE_BMSK 0x7

#define IPA_ENDP_INIT_MODE_N_MODE_SHFT 0x0



#define IPA_ENDP_INIT_HDR_N_OFST_v3_0(n) (0x00000810 + 0x60 * (n))

#define IPA_ENDP_INIT_HDR_N_OFST_v3_0(n) (0x00000810 + 0x70 * (n))

#define IPA_ENDP_INIT_HDR_N_HDR_LEN_BMSK 0x3f

#define IPA_ENDP_INIT_HDR_N_HDR_LEN_SHFT 0x0

#define IPA_ENDP_INIT_HDR_N_HDR_ADDITIONAL_CONST_LEN_BMSK 0x7e000
@@ -114,11 +114,11 @@ 
#define IPA_ENDP_INIT_HDR_N_HDR_OFST_METADATA_SHFT 0x7

#define IPA_ENDP_INIT_HDR_N_HDR_OFST_METADATA_BMSK 0x1f80



#define IPA_ENDP_INIT_NAT_N_OFST_v3_0(n) (0x0000080C + 0x60 * (n))

#define IPA_ENDP_INIT_NAT_N_OFST_v3_0(n) (0x0000080C + 0x70 * (n))

#define IPA_ENDP_INIT_NAT_N_NAT_EN_BMSK 0x3

#define IPA_ENDP_INIT_NAT_N_NAT_EN_SHFT 0x0



#define IPA_ENDP_INIT_HDR_EXT_n_OFST_v3_0(n) (0x00000814 + 0x60 * (n))

#define IPA_ENDP_INIT_HDR_EXT_n_OFST_v3_0(n) (0x00000814 + 0x70 * (n))

#define IPA_ENDP_INIT_HDR_EXT_n_HDR_ENDIANNESS_BMSK 0x1

#define IPA_ENDP_INIT_HDR_EXT_n_HDR_ENDIANNESS_SHFT 0x0

#define IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_VALID_BMSK 0x2
@@ -135,19 +135,19 @@ 
#define IPA_SINGLE_NDP_MODE_OFST 0x00000068

#define IPA_QCNCM_OFST 0x00000064



#define IPA_ENDP_INIT_CTRL_N_OFST(n) (0x00000700 + 0x60 * (n))

#define IPA_ENDP_INIT_CTRL_N_OFST(n) (0x00000800 + 0x70 * (n))

#define IPA_ENDP_INIT_CTRL_N_ENDP_SUSPEND_BMSK 0x1

#define IPA_ENDP_INIT_CTRL_N_ENDP_SUSPEND_SHFT 0x0

#define IPA_ENDP_INIT_CTRL_N_ENDP_DELAY_BMSK 0x2

#define IPA_ENDP_INIT_CTRL_N_ENDP_DELAY_SHFT 0x1



#define IPA_ENDP_INIT_HOL_BLOCK_EN_N_OFST_v3_0(n) (0x0000082c + 0x60 * (n))

#define IPA_ENDP_INIT_HOL_BLOCK_EN_N_OFST_v3_0(n) (0x0000082c + 0x70 * (n))

#define IPA_ENDP_INIT_HOL_BLOCK_EN_N_RMSK 0x1

#define IPA_ENDP_INIT_HOL_BLOCK_EN_N_MAX 19

#define IPA_ENDP_INIT_HOL_BLOCK_EN_N_EN_BMSK 0x1

#define IPA_ENDP_INIT_HOL_BLOCK_EN_N_EN_SHFT 0x0



#define IPA_ENDP_INIT_DEAGGR_n_OFST_v3_0(n) (0x00000834 + 0x60 * (n))

#define IPA_ENDP_INIT_DEAGGR_n_OFST_v3_0(n) (0x00000834 + 0x70 * (n))

#define IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_BMSK 0x3F

#define IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_SHFT 0x0

#define IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_BMSK 0x40
@@ -157,7 +157,7 @@ 
#define IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_BMSK 0xFFFF0000

#define IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_SHFT 0x10



#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_N_OFST_v3_0(n) (0x00000830 + 0x60 * (n))

#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_N_OFST_v3_0(n) (0x00000830 + 0x70 * (n))

#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_N_RMSK 0x1ff

#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_N_MAX 19

#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_N_TIMER_BMSK 0x1ff
@@ -183,13 +183,15 @@ 
#define IPA_DEBUG_CNT_CTRL_N_DBG_CNT_EN_BMSK 0x1

#define IPA_DEBUG_CNT_CTRL_N_DBG_CNT_EN_SHFT 0x0



#define IPA_ENDP_STATUS_n_OFST(n) (0x00000840 + 0x60 * (n))

#define IPA_ENDP_STATUS_n_OFST(n) (0x00000840 + 0x70 * (n))

#define IPA_ENDP_STATUS_n_STATUS_LOCATION_BMSK 0x100

#define IPA_ENDP_STATUS_n_STATUS_LOCATION_SHFT 0x8

#define IPA_ENDP_STATUS_n_STATUS_ENDP_BMSK 0x3e

#define IPA_ENDP_STATUS_n_STATUS_ENDP_SHFT 0x1

#define IPA_ENDP_STATUS_n_STATUS_EN_BMSK 0x1

#define IPA_ENDP_STATUS_n_STATUS_EN_SHFT 0x0



#define IPA_ENDP_INIT_CFG_n_OFST(n) (0x00000808 + 0x60 * (n))

#define IPA_ENDP_INIT_CFG_n_OFST(n) (0x00000808 + 0x70 * (n))

#define IPA_ENDP_INIT_CFG_n_RMSK 0x7f

#define IPA_ENDP_INIT_CFG_n_MAXn 19

#define IPA_ENDP_INIT_CFG_n_CS_METADATA_HDR_OFFSET_BMSK 0x78
@@ -199,18 +201,18 @@ 
#define IPA_ENDP_INIT_CFG_n_FRAG_OFFLOAD_EN_BMSK 0x1

#define IPA_ENDP_INIT_CFG_n_FRAG_OFFLOAD_EN_SHFT 0x0



#define IPA_ENDP_INIT_HDR_METADATA_MASK_n_OFST(n) (0x00000818 + 0x60 * (n))

#define IPA_ENDP_INIT_HDR_METADATA_MASK_n_OFST(n) (0x00000818 + 0x70 * (n))

#define IPA_ENDP_INIT_HDR_METADATA_MASK_n_RMSK 0xffffffff

#define IPA_ENDP_INIT_HDR_METADATA_MASK_n_MAXn 19

#define IPA_ENDP_INIT_HDR_METADATA_MASK_n_METADATA_MASK_BMSK 0xffffffff

#define IPA_ENDP_INIT_HDR_METADATA_MASK_n_METADATA_MASK_SHFT 0x0



#define IPA_ENDP_INIT_HDR_METADATA_n_OFST(n) (0x0000081c + 0x60 * (n))

#define IPA_ENDP_INIT_HDR_METADATA_n_OFST(n) (0x0000081c + 0x70 * (n))

#define IPA_ENDP_INIT_HDR_METADATA_n_MUX_ID_BMASK 0xFF0000

#define IPA_ENDP_INIT_HDR_METADATA_n_MUX_ID_SHFT 0x10





#define IPA_ENDP_INIT_RSRC_GRP_n(n) (0x00000838 + 0x60 * (n))

#define IPA_ENDP_INIT_RSRC_GRP_n(n) (0x00000838 + 0x70 * (n))

#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK 0x7

#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT 0
@@ -240,7 +242,7 @@ 
#define IPA_FILT_ROUT_HASH_FLUSH_IPv6_FILT_SHFT (4)

#define IPA_FILT_ROUT_HASH_FLUSH_IPv6_ROUT_SHFT (0)



#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_OFST(n) (0x00000854 + 0x60 * (n))

#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_OFST(n) (0x0000085C + 0x70 * (n))

#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_ID_SHFT 0

#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_ID_BMSK 0x1

#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_IP_SHFT 1

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

+11 −2
Original line number Diff line number Diff line
@@ -573,6 +573,10 @@ void _ipa_cfg_route_v3_0(struct ipa3_route *route) 
			IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_SHFT,

			IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_BMSK);



	IPA_SETFIELD_IN_REG(reg_val, route->route_def_retain_hdr,

			IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_SHFT,

			IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_BMSK);



	ipa_write_reg(ipa3_ctx->mmio, IPA_ROUTE_OFST_v3_0, reg_val);

}
@@ -2422,6 +2426,10 @@ static void _ipa_cfg_ep_status_v3_0(u32 clnt_hdl, 
			IPA_ENDP_STATUS_n_STATUS_ENDP_SHFT,

			IPA_ENDP_STATUS_n_STATUS_ENDP_BMSK);



	IPA_SETFIELD_IN_REG(reg_val, ep_status->status_location,

			IPA_ENDP_STATUS_n_STATUS_LOCATION_SHFT,

			IPA_ENDP_STATUS_n_STATUS_LOCATION_BMSK);



	ipa_write_reg(ipa3_ctx->mmio,

			IPA_ENDP_STATUS_n_OFST(clnt_hdl),

			reg_val);
@@ -2446,10 +2454,11 @@ int ipa3_cfg_ep_status(u32 clnt_hdl, const struct ipa3_ep_cfg_status *ep_status) 
		return -EINVAL;

	}



	IPADBG("pipe=%d, status_en=%d status_ep=%d\n",

	IPADBG("pipe=%d, status_en=%d status_ep=%d status_location=%d\n",

			clnt_hdl,

			ep_status->status_en,

			ep_status->status_ep);

			ep_status->status_ep,

			ep_status->status_location);



	/* copy over EP cfg */

	ipa3_ctx->ep[clnt_hdl].status = *ep_status;

include/linux/ipa.h

+2 −4
Original line number Diff line number Diff line
@@ -695,16 +695,14 @@ enum ipa_irq_type { 
	IPA_UC_IRQ_3,

	IPA_UC_IN_Q_NOT_EMPTY_IRQ,

	IPA_UC_RX_CMD_Q_NOT_FULL_IRQ,

	IPA_UC_TX_CMD_Q_NOT_FULL_IRQ,

	IPA_UC_TO_PROC_ACK_Q_NOT_FULL_IRQ,

	IPA_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ,

	IPA_RX_ERR_IRQ,

	IPA_DEAGGR_ERR_IRQ,

	IPA_TX_ERR_IRQ,

	IPA_STEP_MODE_IRQ,

	IPA_PROC_ERR_IRQ,

	IPA_TX_SUSPEND_IRQ = 16,

	IPA_TX_HOLB_DROP_IRQ = 17,

	IPA_TX_SUSPEND_IRQ = 14,

	IPA_TX_HOLB_DROP_IRQ = 15,



	IPA_IRQ_MAX

};