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Commit ca68e5b8 authored by Krishna Manikandan's avatar Krishna Manikandan
Browse files

msm: mdss: Use TPG to handle null commit 



Add support to use TPG to send configurable constant color to
panel during the null commit to ensure that no fetch
is happening during the secure to non-secure transition and
vice-versa.

Change-Id: I8cc1a283e88fa9be91da38019c7d532d5180dfb5
Signed-off-by: default avatarKrishna Manikandan <mkrishn@codeaurora.org>
parent 80922117

drivers/video/msm/mdss/mdp3_ctrl.c

+3 −3
Original line number Diff line number Diff line
@@ -462,9 +462,9 @@ static int mdp3_ctrl_async_blit_req(struct msm_fb_data_type *mfd, 
			MDP3_DMA_OUTPUT_SEL_DSI_VIDEO)) {

		rc = wait_for_completion_timeout(&session->secure_completion,

			dma_timeout_value(session->dma));

		if (rc) {

		if (!rc) {

			pr_err("Timed out waiting for completion of secure display\n");

			return rc;

			return -EINVAL;

		}

	}

drivers/video/msm/mdss/mdp3_dma.c

+26 −19
Original line number Diff line number Diff line
@@ -682,27 +682,19 @@ static int mdp3_handle_null_commit(struct mdp3_dma *dma, struct mdp3_intf *intf) 
	int retry_count = 2;

	unsigned long flag;

	int cb_type = MDP3_DMA_CALLBACK_TYPE_VSYNC;

	u32 tpg_cfg = 0, dmap_cfg = 0;



	if (!dma->source_config.format && !dma->source_config.stride) {

		pr_debug("Null commit already handled\n");

		return 0;

	}



	/*

	 * Size and stride are set to 0 to ensure that DMA pipe does not

	 * fetch anything whenever we get a null commit. The values will be

	 * reconfigured to the correct values in the next commit.

	/* To block the fetch start to fetch block, program the TPG

	 * with constant color so that all the transactions are blocked

	 * during the transition from secure to non-secure and vice-versa.

	 */



	MDP3_REG_WRITE(MDP3_REG_DMA_P_SIZE, 0);

	MDP3_REG_WRITE(MDP3_REG_DMA_P_IBUF_Y_STRIDE, 0);

	tpg_cfg = MDP3_REG_READ(MDP3_REG_DSI_VIDEO_TEST_CTL);

	tpg_cfg |= BIT(31);

	MDP3_REG_WRITE(MDP3_REG_DSI_VIDEO_TEST_COL_VAR1, 0);

	MDP3_REG_WRITE(MDP3_REG_DSI_VIDEO_TEST_CTL, tpg_cfg);



	spin_lock_irqsave(&dma->dma_lock, flag);

	dma->source_config.format = 0;

	dma->source_config.stride = 0;

	mdp3_irq_disable(MDP3_INTR_LCDC_UNDERFLOW);

	MDP3_REG_WRITE(MDP3_REG_DSI_VIDEO_UNDERFLOW_CTL, 0x80000000);



	if (!intf->active) {

		pr_debug("%s start interface\n", __func__);

		intf->start(intf);
@@ -718,6 +710,7 @@ static int mdp3_handle_null_commit(struct mdp3_dma *dma, struct mdp3_intf *intf) 
	init_completion(&dma->vsync_comp);

	spin_unlock_irqrestore(&dma->dma_lock, flag);

	mdp3_dma_callback_enable(dma, cb_type);

	dma->update_src_cfg = true;



retry_vsync:

	pr_debug("wait for vsync_comp started\n");
@@ -735,6 +728,12 @@ retry_vsync: 
	}

	pr_debug("wait for vsync_comp done\n");



	dmap_cfg = MDP3_REG_READ(MDP3_REG_DMA_P_CONFIG);

	if (dmap_cfg & BIT(21)) {

		dmap_cfg &= ~BIT(21);

		MDP3_REG_WRITE(MDP3_REG_DMA_P_CONFIG, dmap_cfg);

	}



return rc;



}
@@ -775,6 +774,7 @@ static int mdp3_dmap_update(struct mdp3_dma *dma, void *buf, 
	int rc = 0;

	int retry_count = 2;

	int vsync = 0;

	u32 tpg_cfg = 0;



	ATRACE_BEGIN(__func__);

	pr_debug("mdp3_dmap_update\n");
@@ -804,6 +804,15 @@ static int mdp3_dmap_update(struct mdp3_dma *dma, void *buf, 
	if (dma->ccs_config.ccs_dirty)

		mdp3_ccs_update(dma, true);

	mutex_unlock(&dma->pp_lock);



	if (dma->output_config.out_sel == MDP3_DMA_OUTPUT_SEL_DSI_VIDEO) {

		tpg_cfg = MDP3_REG_READ(MDP3_REG_DSI_VIDEO_TEST_CTL);

		if (tpg_cfg & BIT(31)) {

			tpg_cfg &= ~BIT(31);

			MDP3_REG_WRITE(MDP3_REG_DSI_VIDEO_TEST_CTL, tpg_cfg);

		}

	}



	spin_lock_irqsave(&dma->dma_lock, flag);

	MDP3_REG_WRITE(MDP3_REG_DMA_P_IBUF_ADDR, (u32)(buf +

			dma->roi.y * dma->source_config.stride +
@@ -843,9 +852,6 @@ retry_vsync: 
			rc = -1;

		}

		ATRACE_END("mdp3_wait_for_vsync_comp");



		if (!mdp3_res->irq_ref_count[MDP3_INTR_LCDC_UNDERFLOW])

			mdp3_irq_enable(MDP3_INTR_LCDC_UNDERFLOW);

	}

	pr_debug("$%s wait for vsync_comp out\n", __func__);

	ATRACE_END(__func__);
@@ -1317,6 +1323,7 @@ int dsi_video_config(struct mdp3_intf *intf, struct mdp3_intf_cfg *cfg) 


	v->underflow_color |= 0x80000000;

	MDP3_REG_WRITE(MDP3_REG_DSI_VIDEO_UNDERFLOW_CTL, v->underflow_color);

	MDP3_REG_WRITE(MDP3_REG_DSI_VIDEO_TEST_CTL, 0x70000000);



	return 0;

}