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Commit ca05f29c authored by Yaniv Rosner's avatar Yaniv Rosner Committed by David S. Miller
Browse files

bnx2x: Fix BCM57810-KR FC 



Fix 57810-KR flow-control handling link is achieved via CL37 AN.

Signed-off-by: default avatarYaniv Rosner <yanivr@broadcom.com>
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 27d9129f

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

+27 −0
Original line number Diff line number Diff line
@@ -3655,6 +3655,33 @@ static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy, 
	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {

		bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);

		bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);

	} else if (CHIP_IS_E3(bp) &&

		SINGLE_MEDIA_DIRECT(params)) {

		u8 lane = bnx2x_get_warpcore_lane(phy, params);

		u16 gp_status, gp_mask;

		bnx2x_cl45_read(bp, phy,

				MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,

				&gp_status);

		gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |

			   MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<

			lane;

		if ((gp_status & gp_mask) == gp_mask) {

			bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,

					MDIO_AN_REG_ADV_PAUSE, &ld_pause);

			bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,

					MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);

		} else {

			bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,

					MDIO_AN_REG_CL37_FC_LD, &ld_pause);

			bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,

					MDIO_AN_REG_CL37_FC_LP, &lp_pause);

			ld_pause = ((ld_pause &

				     MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)

				    << 3);

			lp_pause = ((lp_pause &

				     MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)

				    << 3);

		}

	} else {

		bnx2x_cl45_read(bp, phy,

				MDIO_AN_DEVAD,

drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -6944,6 +6944,10 @@ Theotherbitsarereservedandshouldbezero*/ 
#define MDIO_WC_REG_GP2_STATUS_GP_2_2			0x81d2

#define MDIO_WC_REG_GP2_STATUS_GP_2_3			0x81d3

#define MDIO_WC_REG_GP2_STATUS_GP_2_4			0x81d4

#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000

#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100

#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010

#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1

#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP		0x81EE

#define MDIO_WC_REG_UC_INFO_B1_VERSION			0x81F0

#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE		0x81F2