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Commit c9cf73ae authored by Matt Porter's avatar Matt Porter Committed by Linus Torvalds
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[PATCH] ppc32: add 440ep support 



Add PPC440EP core support.  PPC440EP is a PPC440-based SoC with a classic PPC
FPU and another set of peripherals.

Signed-off-by: default avatarWade Farnsworth <wfarnsworth@mvista.com>
Signed-off-by: default avatarMatt Porter <mporter@kernel.crashing.org>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent e8be1c8e

arch/ppc/boot/simple/Makefile

+6 −0
Original line number Diff line number Diff line
@@ -61,6 +61,12 @@ zimageinitrd-$(CONFIG_IBM_OPENBIOS) := zImage.initrd-TREE 
         end-$(CONFIG_EMBEDDEDBOOT)	:= embedded

        misc-$(CONFIG_EMBEDDEDBOOT)	:= misc-embedded.o



      zimage-$(CONFIG_BAMBOO)		:= zImage-TREE

zimageinitrd-$(CONFIG_BAMBOO)		:= zImage.initrd-TREE

         end-$(CONFIG_BAMBOO)		:= bamboo

  entrypoint-$(CONFIG_BAMBOO)		:= 0x01000000

     extra.o-$(CONFIG_BAMBOO)		:= pibs.o



      zimage-$(CONFIG_EBONY)		:= zImage-TREE

zimageinitrd-$(CONFIG_EBONY)		:= zImage.initrd-TREE

         end-$(CONFIG_EBONY)		:= ebony

arch/ppc/boot/simple/pibs.c

+3 −1
Original line number Diff line number Diff line
@@ -91,9 +91,11 @@ load_kernel(unsigned long load_addr, int num_words, unsigned long cksum, 


	mac64 = simple_strtoull((char *)PIBS_MAC_BASE, 0, 16);

	memcpy(hold_residual->bi_enetaddr, (char *)&mac64+2, 6);

#ifdef CONFIG_440GX

#if defined(CONFIG_440GX) || defined(CONFIG_440EP)

	mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET), 0, 16);

	memcpy(hold_residual->bi_enet1addr, (char *)&mac64+2, 6);

#endif

#ifdef CONFIG_440GX

	mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*2), 0, 16);

	memcpy(hold_residual->bi_enet2addr, (char *)&mac64+2, 6);

	mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*3), 0, 16);

arch/ppc/kernel/cputable.c

+20 −0
Original line number Diff line number Diff line
@@ -852,6 +852,26 @@ struct cpu_spec cpu_specs[] = { 


#endif /* CONFIG_40x */

#ifdef CONFIG_44x

	{

		.pvr_mask		= 0xf0000fff,

		.pvr_value		= 0x40000850,

		.cpu_name		= "440EP Rev. A",

		.cpu_features		= CPU_FTR_SPLIT_ID_CACHE |

			CPU_FTR_USE_TB,

		.cpu_user_features	= COMMON_PPC, /* 440EP has an FPU */

		.icache_bsize		= 32,

		.dcache_bsize		= 32,

	},

	{

		.pvr_mask		= 0xf0000fff,

		.pvr_value		= 0x400008d3,

		.cpu_name		= "440EP Rev. B",

		.cpu_features		= CPU_FTR_SPLIT_ID_CACHE |

			CPU_FTR_USE_TB,

		.cpu_user_features	= COMMON_PPC, /* 440EP has an FPU */

		.icache_bsize		= 32,

		.dcache_bsize		= 32,

	},

	{ 	/* 440GP Rev. B */

		.pvr_mask		= 0xf0000fff,

		.pvr_value		= 0x40000440,

arch/ppc/kernel/entry.S

+1 −0
Original line number Diff line number Diff line
@@ -215,6 +215,7 @@ syscall_dotrace_cont: 
	lwzx	r10,r10,r0	/* Fetch system call handler [ptr] */

	mtlr	r10

	addi	r9,r1,STACK_FRAME_OVERHEAD

	PPC440EP_ERR42

	blrl			/* Call handler */

	.globl	ret_from_syscall

ret_from_syscall:

arch/ppc/kernel/head_44x.S

+12 −0
Original line number Diff line number Diff line
@@ -190,7 +190,9 @@ skpinv: addi r4,r4,1 /* Increment */ 


	/* xlat fields */

	lis	r4,UART0_PHYS_IO_BASE@h		/* RPN depends on SoC */

#ifndef CONFIG_440EP

	ori	r4,r4,0x0001		/* ERPN is 1 for second 4GB page */

#endif



	/* attrib fields */

	li	r5,0
@@ -228,6 +230,16 @@ skpinv: addi r4,r4,1 /* Increment */ 
	lis	r4,interrupt_base@h	/* IVPR only uses the high 16-bits */

	mtspr	SPRN_IVPR,r4



#ifdef CONFIG_440EP

	/* Clear DAPUIB flag in CCR0 (enable APU between CPU and FPU) */

	mfspr	r2,SPRN_CCR0

	lis	r3,0xffef

	ori	r3,r3,0xffff

	and	r2,r2,r3

	mtspr	SPRN_CCR0,r2

	isync

#endif



	/*

	 * This is where the main kernel code starts.

	 */