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Commit c9ac1361 authored by Paul Mundt's avatar Paul Mundt
Browse files

Merge branch 'viafb-next' of git://github.com/schandinat/linux-2.6

parents 53b50314 2563afa9

drivers/video/via/chip.h

+0 −9
Original line number Diff line number Diff line
@@ -110,16 +110,13 @@ 
struct tmds_chip_information {

	int tmds_chip_name;

	int tmds_chip_slave_addr;

	int data_mode;

	int output_interface;

	int i2c_port;

	int device_type;

};



struct lvds_chip_information {

	int lvds_chip_name;

	int lvds_chip_slave_addr;

	int data_mode;

	int output_interface;

	int i2c_port;

};
@@ -142,9 +139,6 @@ struct chip_information { 


struct crt_setting_information {

	int iga_path;

	int h_active;

	int v_active;

	int bpp;

	int refresh_rate;

};
@@ -162,8 +156,6 @@ struct lvds_setting_information { 
	int h_active;

	int v_active;

	int bpp;

	int refresh_rate;

	int lcd_panel_id;

	int lcd_panel_hres;

	int lcd_panel_vres;

	int display_method;
@@ -188,7 +180,6 @@ struct GFX_DPA_SETTING { 
};



struct VT1636_DPA_SETTING {

	int PanelSizeID;

	u8 CLK_SEL_ST1;

	u8 CLK_SEL_ST2;

};

drivers/video/via/dvi.c

+3 −1
Original line number Diff line number Diff line
@@ -195,7 +195,9 @@ void viafb_dvi_set_mode(struct VideoModeTable *mode, int mode_bpp, 
	struct crt_mode_table *pDviTiming;

	unsigned long desirePixelClock, maxPixelClock;

	pDviTiming = mode->crtc;

	desirePixelClock = pDviTiming->clk / 1000000;

	desirePixelClock = pDviTiming->refresh_rate

		* pDviTiming->crtc.hor_total * pDviTiming->crtc.ver_total

		/ 1000000;

	maxPixelClock = (unsigned long)viaparinfo->

		tmds_setting_info->max_pixel_clock;

drivers/video/via/hw.c

+370 −402
Original line number Diff line number Diff line
@@ -22,342 +22,290 @@ 
#include <linux/via-core.h>

#include "global.h"



static struct pll_map pll_value[] = {

	{25175000,

		{99, 7, 3},

		{85, 3, 4},	/* ignoring bit difference: 0x00008000 */

		{141, 5, 4},

		{141, 5, 4} },

	{29581000,

		{33, 4, 2},

		{66, 2, 4},	/* ignoring bit difference: 0x00808000 */

		{166, 5, 4},	/* ignoring bit difference: 0x00008000 */

		{165, 5, 4} },

	{26880000,

static struct pll_config cle266_pll_config[] = {

	{19, 4, 0},

	{26, 5, 0},

	{28, 5, 0},

	{31, 5, 0},

	{33, 5, 0},

	{55, 5, 0},

	{102, 5, 0},

	{53, 6, 0},

	{92, 6, 0},

	{98, 6, 0},

	{112, 6, 0},

	{41, 7, 0},

	{60, 7, 0},

	{99, 7, 0},

	{100, 7, 0},

	{83, 8, 0},

	{86, 8, 0},

	{108, 8, 0},

	{87, 9, 0},

	{118, 9, 0},

	{95, 12, 0},

	{115, 12, 0},

	{108, 13, 0},

	{83, 17, 0},

	{67, 20, 0},

	{86, 20, 0},

	{98, 20, 0},

	{121, 24, 0},

	{99, 29, 0},

	{33, 3, 1},

	{15, 4, 1},

		{30, 2, 3},	/* ignoring bit difference: 0x00808000 */

		{150, 5, 4},

		{150, 5, 4} },

	{31500000,

		{53, 3, 3},	/* ignoring bit difference: 0x00008000 */

		{141, 4, 4},	/* ignoring bit difference: 0x00008000 */

		{176, 5, 4},

		{176, 5, 4} },

	{31728000,

	{23, 4, 1},

	{37, 5, 1},

	{83, 5, 1},

	{85, 5, 1},

	{94, 5, 1},

	{103, 5, 1},

	{109, 5, 1},

	{113, 5, 1},

	{121, 5, 1},

	{82, 6, 1},

	{31, 7, 1},

		{177, 5, 4},	/* ignoring bit difference: 0x00008000 */

		{177, 5, 4},

		{142, 4, 4} },

	{32688000,

	{55, 7, 1},

	{84, 7, 1},

	{83, 8, 1},

	{76, 9, 1},

	{127, 9, 1},

	{33, 4, 2},

	{75, 4, 2},

	{119, 4, 2},

	{121, 4, 2},

	{91, 5, 2},

	{118, 5, 2},

	{83, 6, 2},

	{109, 6, 2},

	{90, 7, 2},

	{93, 2, 3},

	{53, 3, 3},

	{73, 4, 3},

		{146, 4, 4},	/* ignoring bit difference: 0x00008000 */

		{183, 5, 4},

		{146, 4, 4} },

	{36000000,

		{101, 5, 3},	/* ignoring bit difference: 0x00008000 */

		{161, 4, 4},	/* ignoring bit difference: 0x00008000 */

		{202, 5, 4},

		{161, 4, 4} },

	{40000000,

	{89, 4, 3},

		{89, 4, 3},	/* ignoring bit difference: 0x00008000 */

		{112, 5, 3},

		{112, 5, 3} },

	{41291000,

		{23, 4, 1},

		{69, 3, 3},	/* ignoring bit difference: 0x00008000 */

		{115, 5, 3},

		{115, 5, 3} },

	{43163000,

		{121, 5, 3},

		{121, 5, 3},	/* ignoring bit difference: 0x00008000 */

	{105, 4, 3},

	{117, 4, 3},

	{101, 5, 3},

	{121, 5, 3},

		{121, 5, 3} },

	{45250000,

	{127, 5, 3},

		{127, 5, 3},	/* ignoring bit difference: 0x00808000 */

	{99, 7, 3}

};



static struct pll_config k800_pll_config[] = {

	{22, 2, 0},

	{28, 3, 0},

	{81, 3, 1},

	{85, 3, 1},

	{98, 3, 1},

	{112, 3, 1},

	{86, 4, 1},

	{166, 4, 1},

	{109, 5, 1},

	{113, 5, 1},

	{121, 5, 1},

	{131, 5, 1},

	{143, 5, 1},

	{153, 5, 1},

	{66, 3, 2},

	{68, 3, 2},

	{95, 3, 2},

	{106, 3, 2},

	{116, 3, 2},

	{93, 4, 2},

	{119, 4, 2},

	{121, 4, 2},

	{133, 4, 2},

	{137, 4, 2},

	{117, 5, 2},

	{118, 5, 2},

	{120, 5, 2},

	{124, 5, 2},

	{132, 5, 2},

	{137, 5, 2},

	{141, 5, 2},

	{166, 5, 2},

	{170, 5, 2},

	{191, 5, 2},

	{206, 5, 2},

	{208, 5, 2},

	{30, 2, 3},

	{69, 3, 3},

	{82, 3, 3},

	{83, 3, 3},

	{109, 3, 3},

	{114, 3, 3},

	{125, 3, 3},

	{89, 4, 3},

	{103, 4, 3},

	{117, 4, 3},

	{126, 4, 3},

	{150, 4, 3},

	{161, 4, 3},

	{121, 5, 3},

	{127, 5, 3},

		{127, 5, 3} },

	{46000000,

		{90, 7, 2},

		{103, 4, 3},	/* ignoring bit difference: 0x00008000 */

		{129, 5, 3},

		{103, 4, 3} },

	{46996000,

		{105, 4, 3},	/* ignoring bit difference: 0x00008000 */

		{131, 5, 3},	/* ignoring bit difference: 0x00808000 */

		{131, 5, 3},	/* ignoring bit difference: 0x00808000 */

		{105, 4, 3} },

	{48000000,

		{67, 20, 0},

		{134, 5, 3},	/* ignoring bit difference: 0x00808000 */

	{131, 5, 3},

	{134, 5, 3},

		{134, 5, 3} },

	{48875000,

		{99, 29, 0},

		{82, 3, 3},	/* ignoring bit difference: 0x00808000 */

		{82, 3, 3},	/* ignoring bit difference: 0x00808000 */

		{137, 5, 3} },

	{49500000,

		{83, 6, 2},

		{83, 3, 3},	/* ignoring bit difference: 0x00008000 */

		{138, 5, 3},

		{83, 3, 3} },

	{52406000,

		{117, 4, 3},

		{117, 4, 3},	/* ignoring bit difference: 0x00008000 */

		{117, 4, 3},

		{88, 3, 3} },

	{52977000,

		{37, 5, 1},

		{148, 5, 3},	/* ignoring bit difference: 0x00808000 */

	{148, 5, 3},

		{148, 5, 3} },

	{56250000,

		{55, 7, 1},	/* ignoring bit difference: 0x00008000 */

		{126, 4, 3},	/* ignoring bit difference: 0x00008000 */

		{157, 5, 3},

		{157, 5, 3} },

	{57275000,

		{0, 0, 0},

		{2, 2, 0},

		{2, 2, 0},

		{157, 5, 3} },	/* ignoring bit difference: 0x00808000 */

	{60466000,

		{76, 9, 1},

		{169, 5, 3},	/* ignoring bit difference: 0x00808000 */

		{169, 5, 3},	/* FIXED: old = {72, 2, 3} */

		{169, 5, 3} },

	{61500000,

		{86, 20, 0},

		{172, 5, 3},	/* ignoring bit difference: 0x00808000 */

	{169, 5, 3},

	{172, 5, 3},

		{172, 5, 3} },

	{65000000,

		{109, 6, 2},	/* ignoring bit difference: 0x00008000 */

		{109, 3, 3},	/* ignoring bit difference: 0x00008000 */

		{109, 3, 3},

		{109, 3, 3} },

	{65178000,

		{91, 5, 2},

		{182, 5, 3},	/* ignoring bit difference: 0x00808000 */

		{109, 3, 3},

		{182, 5, 3} },

	{66750000,

		{75, 4, 2},

		{150, 4, 3},	/* ignoring bit difference: 0x00808000 */

		{150, 4, 3},

		{112, 3, 3} },

	{68179000,

		{19, 4, 0},

		{114, 3, 3},	/* ignoring bit difference: 0x00008000 */

		{190, 5, 3},

		{191, 5, 3} },

	{69924000,

		{83, 17, 0},

		{195, 5, 3},	/* ignoring bit difference: 0x00808000 */

	{182, 5, 3},

	{195, 5, 3},

		{195, 5, 3} },

	{70159000,

		{98, 20, 0},

		{196, 5, 3},	/* ignoring bit difference: 0x00808000 */

	{196, 5, 3},

		{195, 5, 3} },

	{72000000,

		{121, 24, 0},

		{161, 4, 3},	/* ignoring bit difference: 0x00808000 */

		{161, 4, 3},

		{161, 4, 3} },

	{78750000,

		{33, 3, 1},

		{66, 3, 2},	/* ignoring bit difference: 0x00008000 */

	{208, 5, 3},

	{66, 2, 4},

	{85, 3, 4},

	{141, 4, 4},

	{146, 4, 4},

	{161, 4, 4},

	{177, 5, 4}

};



static struct pll_config cx700_pll_config[] = {

	{98, 3, 1},

	{86, 4, 1},

	{109, 5, 1},

	{110, 5, 1},

	{113, 5, 1},

	{121, 5, 1},

	{131, 5, 1},

	{135, 5, 1},

	{142, 5, 1},

	{143, 5, 1},

	{153, 5, 1},

	{187, 5, 1},

	{208, 5, 1},

	{68, 2, 2},

	{95, 3, 2},

	{116, 3, 2},

	{93, 4, 2},

	{119, 4, 2},

	{133, 4, 2},

	{137, 4, 2},

	{151, 4, 2},

	{166, 4, 2},

	{110, 5, 2},

		{110, 5, 2} },

	{80136000,

		{28, 5, 0},

		{68, 3, 2},	/* ignoring bit difference: 0x00008000 */

	{112, 5, 2},

		{112, 5, 2} },

	{83375000,

		{93, 2, 3},

		{93, 4, 2},	/* ignoring bit difference: 0x00800000 */

		{93, 4, 2},	/* ignoring bit difference: 0x00800000 */

		{117, 5, 2} },

	{83950000,

		{41, 7, 0},

		{117, 5, 2},	/* ignoring bit difference: 0x00008000 */

	{117, 5, 2},

		{117, 5, 2} },

	{84750000,

	{118, 5, 2},

		{118, 5, 2},	/* ignoring bit difference: 0x00808000 */

		{118, 5, 2},

		{118, 5, 2} },

	{85860000,

		{84, 7, 1},

		{120, 5, 2},	/* ignoring bit difference: 0x00808000 */

	{120, 5, 2},

		{118, 5, 2} },

	{88750000,

		{31, 5, 0},

		{124, 5, 2},	/* ignoring bit difference: 0x00808000 */

		{174, 7, 2},	/* ignoring bit difference: 0x00808000 */

		{124, 5, 2} },

	{94500000,

		{33, 5, 0},

		{132, 5, 2},	/* ignoring bit difference: 0x00008000 */

	{132, 5, 2},

		{132, 5, 2} },

	{97750000,

		{82, 6, 1},

		{137, 5, 2},	/* ignoring bit difference: 0x00808000 */

	{137, 5, 2},

		{137, 5, 2} },

	{101000000,

		{127, 9, 1},

		{141, 5, 2},	/* ignoring bit difference: 0x00808000 */

	{141, 5, 2},

		{141, 5, 2} },

	{106500000,

		{119, 4, 2},

		{119, 4, 2},	/* ignoring bit difference: 0x00808000 */

		{119, 4, 2},

		{149, 5, 2} },

	{108000000,

		{121, 4, 2},

		{121, 4, 2},	/* ignoring bit difference: 0x00808000 */

	{151, 5, 2},

		{151, 5, 2} },

	{113309000,

		{95, 12, 0},

		{95, 3, 2},	/* ignoring bit difference: 0x00808000 */

		{95, 3, 2},

		{159, 5, 2} },

	{118840000,

		{83, 5, 1},

		{166, 5, 2},	/* ignoring bit difference: 0x00808000 */

	{166, 5, 2},

		{166, 5, 2} },

	{119000000,

		{108, 13, 0},

		{133, 4, 2},	/* ignoring bit difference: 0x00808000 */

		{133, 4, 2},

		{167, 5, 2} },

	{121750000,

		{85, 5, 1},

		{170, 5, 2},	/* ignoring bit difference: 0x00808000 */

		{68, 2, 2},

		{0, 0, 0} },

	{125104000,

		{53, 6, 0},	/* ignoring bit difference: 0x00008000 */

		{106, 3, 2},	/* ignoring bit difference: 0x00008000 */

	{175, 5, 2},

		{0, 0, 0} },

	{135000000,

		{94, 5, 1},

		{28, 3, 0},	/* ignoring bit difference: 0x00804000 */

		{151, 4, 2},

		{189, 5, 2} },

	{136700000,

		{115, 12, 0},

		{191, 5, 2},	/* ignoring bit difference: 0x00808000 */

	{191, 5, 2},

		{191, 5, 2} },

	{138400000,

		{87, 9, 0},

		{116, 3, 2},	/* ignoring bit difference: 0x00808000 */

		{116, 3, 2},

		{194, 5, 2} },

	{146760000,

		{103, 5, 1},

		{206, 5, 2},	/* ignoring bit difference: 0x00808000 */

	{206, 5, 2},

		{206, 5, 2} },

	{153920000,

		{86, 8, 0},

		{86, 4, 1},	/* ignoring bit difference: 0x00808000 */

	{174, 7, 2},

	{82, 3, 3},

	{109, 3, 3},

	{117, 4, 3},

	{150, 4, 3},

	{161, 4, 3},

	{112, 5, 3},

	{115, 5, 3},

	{121, 5, 3},

	{127, 5, 3},

	{129, 5, 3},

	{131, 5, 3},

	{134, 5, 3},

	{138, 5, 3},

	{148, 5, 3},

	{157, 5, 3},

	{169, 5, 3},

	{172, 5, 3},

	{190, 5, 3},

	{195, 5, 3},

	{196, 5, 3},

	{208, 5, 3},

	{141, 5, 4},

	{150, 5, 4},

	{166, 5, 4},

	{176, 5, 4},

	{177, 5, 4},

	{183, 5, 4},

	{202, 5, 4}

};



static struct pll_config vx855_pll_config[] = {

	{86, 4, 1},

		{86, 4, 1} },	/* FIXED: old = {84, 2, 1} */

	{156000000,

		{109, 5, 1},

		{109, 5, 1},	/* ignoring bit difference: 0x00808000 */

		{109, 5, 1},

		{108, 5, 1} },

	{157500000,

		{55, 5, 0},	/* ignoring bit difference: 0x00008000 */

		{22, 2, 0},	/* ignoring bit difference: 0x00802000 */

	{108, 5, 1},

	{110, 5, 1},

		{110, 5, 1} },

	{162000000,

	{113, 5, 1},

		{113, 5, 1},	/* ignoring bit difference: 0x00808000 */

		{113, 5, 1},

		{113, 5, 1} },

	{187000000,

		{118, 9, 0},

		{131, 5, 1},	/* ignoring bit difference: 0x00808000 */

	{121, 5, 1},

	{131, 5, 1},

		{131, 5, 1} },

	{193295000,

		{108, 8, 0},

		{81, 3, 1},	/* ignoring bit difference: 0x00808000 */

	{135, 5, 1},

		{135, 5, 1} },

	{202500000,

		{99, 7, 0},

		{85, 3, 1},	/* ignoring bit difference: 0x00808000 */

	{142, 5, 1},

		{142, 5, 1} },

	{204000000,

		{100, 7, 0},

		{143, 5, 1},	/* ignoring bit difference: 0x00808000 */

	{143, 5, 1},

		{143, 5, 1} },

	{218500000,

		{92, 6, 0},

		{153, 5, 1},	/* ignoring bit difference: 0x00808000 */

	{153, 5, 1},

		{153, 5, 1} },

	{234000000,

		{98, 6, 0},

		{98, 3, 1},	/* ignoring bit difference: 0x00008000 */

		{98, 3, 1},

		{164, 5, 1} },

	{267250000,

		{112, 6, 0},

		{112, 3, 1},	/* ignoring bit difference: 0x00808000 */

	{164, 5, 1},

	{187, 5, 1},

		{187, 5, 1} },

	{297500000,

		{102, 5, 0},	/* ignoring bit difference: 0x00008000 */

		{166, 4, 1},	/* ignoring bit difference: 0x00008000 */

	{208, 5, 1},

		{208, 5, 1} },

	{74481000,

		{26, 5, 0},

		{125, 3, 3},	/* ignoring bit difference: 0x00808000 */

		{208, 5, 3},

		{209, 5, 3} },

	{172798000,

		{121, 5, 1},

		{121, 5, 1},	/* ignoring bit difference: 0x00808000 */

		{121, 5, 1},

		{121, 5, 1} },

	{122614000,

		{60, 7, 0},

		{137, 4, 2},	/* ignoring bit difference: 0x00808000 */

		{137, 4, 2},

		{172, 5, 2} },

	{74270000,

		{83, 8, 1},

		{208, 5, 3},

		{208, 5, 3},

		{0, 0, 0} },

	{148500000,

		{83, 8, 0},

	{110, 5, 2},

	{112, 5, 2},

	{117, 5, 2},

	{118, 5, 2},

	{124, 5, 2},

	{132, 5, 2},

	{137, 5, 2},

	{141, 5, 2},

	{149, 5, 2},

	{151, 5, 2},

	{159, 5, 2},

	{166, 5, 2},

	{167, 5, 2},

	{172, 5, 2},

	{189, 5, 2},

	{191, 5, 2},

	{194, 5, 2},

	{206, 5, 2},

	{208, 5, 2},

		{166, 4, 2},

		{208, 5, 2} }

	{83, 3, 3},

	{88, 3, 3},

	{109, 3, 3},

	{112, 3, 3},

	{103, 4, 3},

	{105, 4, 3},

	{161, 4, 3},

	{112, 5, 3},

	{115, 5, 3},

	{121, 5, 3},

	{127, 5, 3},

	{134, 5, 3},

	{137, 5, 3},

	{148, 5, 3},

	{157, 5, 3},

	{169, 5, 3},

	{172, 5, 3},

	{182, 5, 3},

	{191, 5, 3},

	{195, 5, 3},

	{209, 5, 3},

	{142, 4, 4},

	{146, 4, 4},

	{161, 4, 4},

	{141, 5, 4},

	{150, 5, 4},

	{165, 5, 4},

	{176, 5, 4}

};



/* according to VIA Technologies these values are based on experiment */

static struct io_reg scaling_parameters[] = {

	{VIACR, CR7A, 0xFF, 0x01},	/* LCD Scaling Parameter 1 */

	{VIACR, CR7B, 0xFF, 0x02},	/* LCD Scaling Parameter 2 */

	{VIACR, CR7C, 0xFF, 0x03},	/* LCD Scaling Parameter 3 */

	{VIACR, CR7D, 0xFF, 0x04},	/* LCD Scaling Parameter 4 */

	{VIACR, CR7E, 0xFF, 0x07},	/* LCD Scaling Parameter 5 */

	{VIACR, CR7F, 0xFF, 0x0A},	/* LCD Scaling Parameter 6 */

	{VIACR, CR80, 0xFF, 0x0D},	/* LCD Scaling Parameter 7 */

	{VIACR, CR81, 0xFF, 0x13},	/* LCD Scaling Parameter 8 */

	{VIACR, CR82, 0xFF, 0x16},	/* LCD Scaling Parameter 9 */

	{VIACR, CR83, 0xFF, 0x19},	/* LCD Scaling Parameter 10 */

	{VIACR, CR84, 0xFF, 0x1C},	/* LCD Scaling Parameter 11 */

	{VIACR, CR85, 0xFF, 0x1D},	/* LCD Scaling Parameter 12 */

	{VIACR, CR86, 0xFF, 0x1E},	/* LCD Scaling Parameter 13 */

	{VIACR, CR87, 0xFF, 0x1F},	/* LCD Scaling Parameter 14 */

};



static struct fifo_depth_select display_fifo_depth_reg = {
@@ -751,7 +699,7 @@ void viafb_unlock_crt(void) 
	viafb_write_reg_mask(CR47, VIACR, 0, BIT0);

}



void write_dac_reg(u8 index, u8 r, u8 g, u8 b)

static void write_dac_reg(u8 index, u8 r, u8 g, u8 b)

{

	outb(index, LUT_INDEX_WRITE);

	outb(r, LUT_DATA);
@@ -1674,44 +1622,64 @@ static u32 vx855_encode_pll(struct pll_config pll) 
		| pll.multiplier;

}



static inline u32 get_pll_internal_frequency(u32 ref_freq,

	struct pll_config pll)

{

	return ref_freq / pll.divisor * pll.multiplier;

}



static inline u32 get_pll_output_frequency(u32 ref_freq, struct pll_config pll)

{

	return get_pll_internal_frequency(ref_freq, pll)>>pll.rshift;

}



static struct pll_config get_pll_config(struct pll_config *config, int size,

	int clk)

{

	struct pll_config best = config[0];

	const u32 f0 = 14318180; /* X1 frequency */

	int i;



	for (i = 1; i < size; i++) {

		if (abs(get_pll_output_frequency(f0, config[i]) - clk)

			< abs(get_pll_output_frequency(f0, best) - clk))

			best = config[i];

	}



	return best;

}



u32 viafb_get_clk_value(int clk)

{

	u32 value = 0;

	int i = 0;



	while (i < NUM_TOTAL_PLL_TABLE && clk != pll_value[i].clk)

		i++;



	if (i == NUM_TOTAL_PLL_TABLE) {

		printk(KERN_WARNING "viafb_get_clk_value: PLL lookup failed!");

	} else {

	switch (viaparinfo->chip_info->gfx_chip_name) {

	case UNICHROME_CLE266:

	case UNICHROME_K400:

			value = cle266_encode_pll(pll_value[i].cle266_pll);

		value = cle266_encode_pll(get_pll_config(cle266_pll_config,

			ARRAY_SIZE(cle266_pll_config), clk));

		break;



	case UNICHROME_K800:

	case UNICHROME_PM800:

	case UNICHROME_CN700:

			value = k800_encode_pll(pll_value[i].k800_pll);

		value = k800_encode_pll(get_pll_config(k800_pll_config,

			ARRAY_SIZE(k800_pll_config), clk));

		break;



	case UNICHROME_CX700:

	case UNICHROME_CN750:

	case UNICHROME_K8M890:

	case UNICHROME_P4M890:

	case UNICHROME_P4M900:

	case UNICHROME_VX800:

			value = k800_encode_pll(pll_value[i].cx700_pll);

		value = k800_encode_pll(get_pll_config(cx700_pll_config,

			ARRAY_SIZE(cx700_pll_config), clk));

		break;



	case UNICHROME_VX855:

	case UNICHROME_VX900:

			value = vx855_encode_pll(pll_value[i].vx855_pll);

		value = vx855_encode_pll(get_pll_config(vx855_pll_config,

			ARRAY_SIZE(vx855_pll_config), clk));

		break;

	}

	}



	return value;

}
@@ -2034,7 +2002,7 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, 
	int i;

	int index = 0;

	int h_addr, v_addr;

	u32 pll_D_N;

	u32 pll_D_N, clock;



	for (i = 0; i < video_mode->mode_array; i++) {

		index = i;
@@ -2087,7 +2055,9 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, 
	    && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))

		viafb_load_FIFO_reg(set_iga, h_addr, v_addr);



	pll_D_N = viafb_get_clk_value(crt_table[index].clk);

	clock = crt_reg.hor_total * crt_reg.ver_total

		* crt_table[index].refresh_rate;

	pll_D_N = viafb_get_clk_value(clock);

	DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);

	viafb_set_vclock(pll_D_N, set_iga);
@@ -2117,9 +2087,6 @@ void viafb_update_device_setting(int hres, int vres, 
	int bpp, int vmode_refresh, int flag)

{

	if (flag == 0) {

		viaparinfo->crt_setting_info->h_active = hres;

		viaparinfo->crt_setting_info->v_active = vres;

		viaparinfo->crt_setting_info->bpp = bpp;

		viaparinfo->crt_setting_info->refresh_rate =

			vmode_refresh;
@@ -2129,13 +2096,9 @@ void viafb_update_device_setting(int hres, int vres, 
		viaparinfo->lvds_setting_info->h_active = hres;

		viaparinfo->lvds_setting_info->v_active = vres;

		viaparinfo->lvds_setting_info->bpp = bpp;

		viaparinfo->lvds_setting_info->refresh_rate =

			vmode_refresh;

		viaparinfo->lvds_setting_info2->h_active = hres;

		viaparinfo->lvds_setting_info2->v_active = vres;

		viaparinfo->lvds_setting_info2->bpp = bpp;

		viaparinfo->lvds_setting_info2->refresh_rate =

			vmode_refresh;

	} else {



		if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
@@ -2147,15 +2110,11 @@ void viafb_update_device_setting(int hres, int vres, 
			viaparinfo->lvds_setting_info->h_active = hres;

			viaparinfo->lvds_setting_info->v_active = vres;

			viaparinfo->lvds_setting_info->bpp = bpp;

			viaparinfo->lvds_setting_info->refresh_rate =

				vmode_refresh;

		}

		if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {

			viaparinfo->lvds_setting_info2->h_active = hres;

			viaparinfo->lvds_setting_info2->v_active = vres;

			viaparinfo->lvds_setting_info2->bpp = bpp;

			viaparinfo->lvds_setting_info2->refresh_rate =

				vmode_refresh;

		}

	}

}
@@ -2430,6 +2389,7 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp, 
		break;

	}



	viafb_write_regx(scaling_parameters, ARRAY_SIZE(scaling_parameters));

	device_off();

	via_set_state(devices, VIA_STATE_OFF);
@@ -2608,35 +2568,43 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp, 
int viafb_get_pixclock(int hres, int vres, int vmode_refresh)

{

	int i;

	struct crt_mode_table *best;

	struct VideoModeTable *vmode = viafb_get_mode(hres, vres);



	for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {

		if ((hres == res_map_refresh_tbl[i].hres)

		    && (vres == res_map_refresh_tbl[i].vres)

		    && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))

			return res_map_refresh_tbl[i].pixclock;

	}

	if (!vmode)

		return RES_640X480_60HZ_PIXCLOCK;



	best = &vmode->crtc[0];

	for (i = 1; i < vmode->mode_array; i++) {

		if (abs(vmode->crtc[i].refresh_rate - vmode_refresh)

			< abs(best->refresh_rate - vmode_refresh))

			best = &vmode->crtc[i];

	}



	return 1000000000 / (best->crtc.hor_total * best->crtc.ver_total)

		* 1000 / best->refresh_rate;

}



int viafb_get_refresh(int hres, int vres, u32 long_refresh)

{

#define REFRESH_TOLERANCE 3

	int i, nearest = -1, diff = REFRESH_TOLERANCE;

	for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {

		if ((hres == res_map_refresh_tbl[i].hres)

		    && (vres == res_map_refresh_tbl[i].vres)

		    && (diff > (abs(long_refresh -

		    res_map_refresh_tbl[i].vmode_refresh)))) {

			diff = abs(long_refresh - res_map_refresh_tbl[i].

				vmode_refresh);

			nearest = i;

		}

	}

#undef REFRESH_TOLERANCE

	if (nearest > 0)

		return res_map_refresh_tbl[nearest].vmode_refresh;

	int i;

	struct crt_mode_table *best;

	struct VideoModeTable *vmode = viafb_get_mode(hres, vres);



	if (!vmode)

		return 60;



	best = &vmode->crtc[0];

	for (i = 1; i < vmode->mode_array; i++) {

		if (abs(vmode->crtc[i].refresh_rate - long_refresh)

			< abs(best->refresh_rate - long_refresh))

			best = &vmode->crtc[i];

	}



	if (abs(best->refresh_rate - long_refresh) > 3)

		return 60;



	return best->refresh_rate;

}



static void device_off(void)

drivers/video/via/hw.h

+0 −2
Original line number Diff line number Diff line
@@ -893,8 +893,6 @@ struct iga2_crtc_timing { 
/* VT3410 chipset*/

#define VX900_FUNCTION3     0x3410



#define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)



struct IODATA {

	u8 Index;

	u8 Mask;

drivers/video/via/lcd.c

+18 −65

File changed.

Preview size limit exceeded, changes collapsed.