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Commit c99e69e7 authored by Pramod Gurav's avatar Pramod Gurav
Browse files

ARM: dts: msm: Fix cpu-release-addr from enabled address range 



The MSMTITANIUM is expected to have only 2 GB DDR at SOD. Hence choose
an address for cpu-release-addr from available DDR.
Also enable UART on MSMTITANIUM RUMI.

Change-Id: Ie8b8f6d5c08fc0becb985e9075c97eab7c0bb744
Signed-off-by: default avatarPramod Gurav <gpramod@codeaurora.org>
parent 62eb03b5

arch/arm/boot/dts/qcom/msmtitanium-cpu.dtsi

+8 −8
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ 
			compatible = "arm,cortex-a53";

			reg = <0x0>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x46000000>;

			cpu-release-addr = <0x0 0x90000000>;

			qcom,acc = <&acc0>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {
@@ -67,7 +67,7 @@ 
			compatible = "arm,cortex-a53";

			reg = <0x1>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x46000000>;

			cpu-release-addr = <0x0 0x90000000>;

			qcom,acc = <&acc1>;

			next-level-cache = <&L2_0>;

		};
@@ -77,7 +77,7 @@ 
			compatible = "arm,cortex-a53";

			reg = <0x2>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x46000000>;

			cpu-release-addr = <0x0 0x90000000>;

			qcom,acc = <&acc2>;

			next-level-cache = <&L2_0>;

		};
@@ -87,7 +87,7 @@ 
			compatible = "arm,cortex-a53";

			reg = <0x3>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x46000000>;

			cpu-release-addr = <0x0 0x90000000>;

			qcom,acc = <&acc3>;

			next-level-cache = <&L2_0>;

		};
@@ -97,7 +97,7 @@ 
			compatible = "arm,cortex-a53";

			reg = <0x100>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x46000000>;

			cpu-release-addr = <0x0 0x90000000>;

			qcom,acc = <&acc4>;

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {
@@ -112,7 +112,7 @@ 
			compatible = "arm,cortex-a53";

			reg = <0x101>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x46000000>;

			cpu-release-addr = <0x0 0x90000000>;

			qcom,acc = <&acc5>;

			next-level-cache = <&L2_1>;

		};
@@ -122,7 +122,7 @@ 
			compatible = "arm,cortex-a53";

			reg = <0x102>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x46000000>;

			cpu-release-addr = <0x0 0x90000000>;

			qcom,acc = <&acc6>;

			next-level-cache = <&L2_1>;

		};
@@ -132,7 +132,7 @@ 
			compatible = "arm,cortex-a53";

			reg = <0x103>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x46000000>;

			cpu-release-addr = <0x0 0x90000000>;

			qcom,acc = <&acc7>;

			next-level-cache = <&L2_1>;

		};

arch/arm/boot/dts/qcom/msmtitanium-rumi.dts

+5 −1
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 


/dts-v1/;



/memreserve/ 0x46000000 0x00000200;

/memreserve/ 0x90000000 0x00000200;



#include "msmtitanium.dtsi"
@@ -28,3 +28,7 @@ 
		clock-frequency = <10000000>;

	};

};



&blsp1_uart2 {

	status = "ok";

};