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Commit c98f5062 authored by Akash Goel's avatar Akash Goel Committed by Daniel Vetter
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drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv 



For disabling L3 clock gating we need to set bit 25 of MMIO
register 940c. Earlier this was being done by just writing 1
into bit 25 and resetting all other bits.
This patch modifies the routine to read-modify-write of the
register, so that the values of other bits are not destroyed.

v2: Modifying the comments and the patch commit message (Chris)

Signed-off-by: default avatarAkash Goel <akash.goel@intel.com>
Signed-off-by: default avatarSourab Gupta <sourab.gupta@intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
[danvet: Apply checkpatch fixup.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 2ab8b458

drivers/gpu/drm/i915/intel_pm.c

+5 −2
Original line number Original line Diff line number Diff line
@@ -5348,8 +5348,11 @@ static void valleyview_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(GEN6_UCGCTL2,

	I915_WRITE(GEN6_UCGCTL2,

		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);

		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);





	/* WaDisableL3Bank2xClockGate:vlv */

	/* WaDisableL3Bank2xClockGate:vlv

	I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);

	 * Disabling L3 clock gating- MMIO 940c[25] = 1

	 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */

	I915_WRITE(GEN7_UCGCTL4,

		   I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);





	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);

	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);