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Commit c985d7e3 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'zynq/core-smp' of git://git.xilinx.com/linux-xlnx into next/soc2

From Michal Simek <michal.simek@xilinx.com>:

This branch is based on zynq/clksrc/cleanup parts because
there are some dependencies on moving timer to generic location.

I could based it on standard Linux tagged version but you will get
several conflicts you will have to resolve.
If you are OK to resolving these problems, please let me know
I will create another branch with core-smp changes which are not based
on zynq/clksrc/cleanup branch.

* 'zynq/core-smp' of git://git.xilinx.com/linux-xlnx

:
  arm: zynq: Add hotplug support
  arm: zynq: Add smp support
  arm: zynq: Add smp_twd timer
  arm: zynq: Get rid of xilinx function prefix
  arm: zynq: Add support for system reset
  arm: zynq: Move slcr initialization to separate file
  arm: zynq: Load scu baseaddress at run time

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents e382328a c7c28b0f
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+17 −0
Original line number Diff line number Diff line
Cadence TTC - Triple Timer Counter

Required properties:
- compatible : Should be "cdns,ttc".
- reg : Specifies base physical address and size of the registers.
- interrupts : A list of 3 interrupts; one per timer channel.
- clocks: phandle to the source clock

Example:

ttc0: ttc0@f8001000 {
	interrupt-parent = <&intc>;
	interrupts = < 0 10 4 0 11 4 0 12 4 >;
	compatible = "cdns,ttc";
	reg = <0xF8001000 0x1000>;
	clocks = <&cpu_clk 3>;
};
+1 −0
Original line number Diff line number Diff line
@@ -1593,6 +1593,7 @@ config HAVE_ARM_ARCH_TIMER
config HAVE_ARM_TWD
	bool
	depends on SMP
	select CLKSRC_OF if OF
	help
	  This options enables support for the ARM timer and watchdog unit

+13 −39
Original line number Diff line number Diff line
@@ -111,56 +111,30 @@
		};

		ttc0: ttc0@f8001000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "xlnx,ttc";
			interrupt-parent = <&intc>;
			interrupts = < 0 10 4 0 11 4 0 12 4 >;
			compatible = "cdns,ttc";
			reg = <0xF8001000 0x1000>;
			clocks = <&cpu_clk 3>;
			clock-names = "cpu_1x";
			clock-ranges;

			ttc0_0: ttc0.0 {
				status = "disabled";
				reg = <0>;
				interrupts = <0 10 4>;
			};
			ttc0_1: ttc0.1 {
				status = "disabled";
				reg = <1>;
				interrupts = <0 11 4>;
			};
			ttc0_2: ttc0.2 {
				status = "disabled";
				reg = <2>;
				interrupts = <0 12 4>;
			};
		};

		ttc1: ttc1@f8002000 {
			#interrupt-parent = <&intc>;
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "xlnx,ttc";
			interrupt-parent = <&intc>;
			interrupts = < 0 37 4 0 38 4 0 39 4 >;
			compatible = "cdns,ttc";
			reg = <0xF8002000 0x1000>;
			clocks = <&cpu_clk 3>;
			clock-names = "cpu_1x";
			clock-ranges;

			ttc1_0: ttc1.0 {
				status = "disabled";
				reg = <0>;
				interrupts = <0 37 4>;
			};
			ttc1_1: ttc1.1 {
				status = "disabled";
				reg = <1>;
				interrupts = <0 38 4>;
			};
			ttc1_2: ttc1.2 {
				status = "disabled";
				reg = <2>;
				interrupts = <0 39 4>;
		};
		scutimer: scutimer@f8f00600 {
			interrupt-parent = <&intc>;
			interrupts = < 1 13 0x301 >;
			compatible = "arm,cortex-a9-twd-timer";
			reg = < 0xf8f00600 0x20 >;
			clocks = <&cpu_clk 1>;
		} ;
	};
};
+0 −10
Original line number Diff line number Diff line
@@ -32,13 +32,3 @@
&ps_clk {
	clock-frequency = <33333330>;
};

&ttc0_0 {
	status = "ok";
	compatible = "xlnx,ttc-counter-clocksource";
};

&ttc0_1 {
	status = "ok";
	compatible = "xlnx,ttc-counter-clockevent";
};
+0 −8
Original line number Diff line number Diff line
@@ -34,12 +34,4 @@ struct twd_local_timer name __initdata = { \

int twd_local_timer_register(struct twd_local_timer *);

#ifdef CONFIG_HAVE_ARM_TWD
void twd_local_timer_of_register(void);
#else
static inline void twd_local_timer_of_register(void)
{
}
#endif

#endif
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