Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c9840daa authored by Eric Miao's avatar Eric Miao
Browse files

[ARM] pxa: correct SSCR0_SCR to support multiple SoCs 



The previous definitions of SSCR0_SCR and SSCR0_SerClkDiv() prevented
them being used simultaneously when supporting multiple PXA SoCs, esp.
in drivers/spi/pxa2xx_spi.c, make them correct.

The change from SSCR0_SerClkDiv(2) to SSCR0_SCR(2), will make the result
a little bit different in pxa2xx_spi_probe(), however, since that's only
used as a default initialization value, it's acceptable.

Signed-off-by: default avatarEric Miao <eric.y.miao@gmail.com>
parent 793ffb9e

arch/arm/mach-pxa/include/mach/regs-ssp.h

+1 −8
Original line number Diff line number Diff line
@@ -33,14 +33,7 @@ 
#define SSCR0_National	(0x2 << 4)	/* National Microwire */

#define SSCR0_ECS	(1 << 6)	/* External clock select */

#define SSCR0_SSE	(1 << 7)	/* Synchronous Serial Port Enable */



#if defined(CONFIG_PXA25x)

#define SSCR0_SCR	(0x0000ff00)	/* Serial Clock Rate (mask) */

#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */

#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)

#define SSCR0_SCR	(0x000fff00)	/* Serial Clock Rate (mask) */

#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */

#endif

#define SSCR0_SCR(x)	((x) << 8)	/* Serial Clock Rate (mask) */



#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)

#define SSCR0_EDSS	(1 << 20)	/* Extended data size select */

drivers/spi/pxa2xx_spi.c

+7 −7
Original line number Diff line number Diff line
@@ -1319,12 +1319,12 @@ static int setup(struct spi_device *spi) 
	if (drv_data->ssp_type != PXA25x_SSP)

		dev_dbg(&spi->dev, "%ld Hz actual, %s\n",

			clk_get_rate(ssp->clk)

					/ (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),

				/ (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),

			chip->enable_dma ? "DMA" : "PIO");

	else

		dev_dbg(&spi->dev, "%ld Hz actual, %s\n",

			clk_get_rate(ssp->clk) / 2

					/ (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),

				/ (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),

			chip->enable_dma ? "DMA" : "PIO");



	if (spi->bits_per_word <= 8) {
@@ -1558,7 +1558,7 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev) 
	write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |

				SSCR1_TxTresh(TX_THRESH_DFLT),

				drv_data->ioaddr);

	write_SSCR0(SSCR0_SerClkDiv(2)

	write_SSCR0(SSCR0_SCR(2)

			| SSCR0_Motorola

			| SSCR0_DataSize(8),

			drv_data->ioaddr);