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Commit c98158ed authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC fixes from Arnd Bergmann:
 "A nice small set of bug fixes for arm-soc:

   - two incorrect register addresses in DT files on shmobile and hisilicon
   - one revert for a regression on omap
   - one bug fix for a newly introduced pin controller binding
   - one regression fix for the memory controller on omap
   - one patch to avoid a harmless WARN_ON"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: dts: Revert enabling of twl configuration for n900
  ARM: dts: fix L2 address in Hi3620
  ARM: OMAP2+: gpmc: fix gpmc_hwecc_bch_capable()
  pinctrl: dra: dt-bindings: Fix pull enable/disable
  ARM: shmobile: r8a7791: Fix SD2CKCR register address
  ARM: OMAP2+: l2c: squelch warning dump on power control setting
parents 0ef13515 a1ae5b12

arch/arm/boot/dts/hi3620.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -73,7 +73,7 @@ 


		L2: l2-cache {

			compatible = "arm,pl310-cache";

			reg = <0xfc10000 0x100000>;

			reg = <0x100000 0x100000>;

			interrupts = <0 15 4>;

			cache-unified;

			cache-level = <2>;

arch/arm/boot/dts/omap3-n900.dts

+1 −1
Original line number Diff line number Diff line
@@ -353,7 +353,7 @@ 
	};



	twl_power: power {

		compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off";

		compatible = "ti,twl4030-power-n900";

		ti,use_poweroff;

	};

};

arch/arm/boot/dts/r8a7791.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -540,9 +540,9 @@ 
			#clock-cells = <0>;

			clock-output-names = "sd1";

		};

		sd2_clk: sd3_clk@e615007c {

		sd2_clk: sd3_clk@e615026c {

			compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";

			reg = <0 0xe615007c 0 4>;

			reg = <0 0xe615026c 0 4>;

			clocks = <&pll1_div2_clk>;

			#clock-cells = <0>;

			clock-output-names = "sd2";

arch/arm/mach-omap2/gpmc-nand.c

+10 −8
Original line number Diff line number Diff line
@@ -50,6 +50,16 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) 
		 soc_is_omap54xx() || soc_is_dra7xx())

		return 1;



	if (ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW ||

		 ecc_opt == OMAP_ECC_BCH8_CODE_HW_DETECTION_SW) {

		if (cpu_is_omap24xx())

			return 0;

		else if (cpu_is_omap3630() && (GET_OMAP_REVISION() == 0))

			return 0;

		else

			return 1;

	}



	/* OMAP3xxx do not have ELM engine, so cannot support ECC schemes

	 * which require H/W based ECC error detection */

	if ((cpu_is_omap34xx() || cpu_is_omap3630()) &&
@@ -57,14 +67,6 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) 
		 (ecc_opt == OMAP_ECC_BCH8_CODE_HW)))

		return 0;



	/*

	 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1

	 * and AM33xx derivates. Other chips may be added if confirmed to work.

	 */

	if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW) &&

	    (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)))

		return 0;



	/* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */

	if (ecc_opt == OMAP_ECC_HAM1_CODE_HW)

		return 1;

arch/arm/mach-omap2/omap4-common.c

+4 −0
Original line number Diff line number Diff line
@@ -168,6 +168,10 @@ static void omap4_l2c310_write_sec(unsigned long val, unsigned reg) 
		smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;

		break;



	case L310_POWER_CTRL:

		pr_info_once("OMAP L2C310: ROM does not support power control setting\n");

		return;



	default:

		WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);

		return;