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Commit c9774aa7 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "clk: msm: clock-gcc-californium: Rename some clocks"

parents b1b0258c efa7623a

drivers/clk/msm/clock-gcc-californium.c

+6 −6
Original line number Diff line number Diff line
@@ -177,9 +177,9 @@ static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL); 
#define QUSB_REF_CLK_EN                                  (0x41030)

#define DCC_CBCR                                         (0x77004)



DEFINE_CLK_RPM_SMD_BRANCH(xo, xo_ao, RPM_MISC_CLK_TYPE,

DEFINE_CLK_RPM_SMD_BRANCH(xo, xo_a_clk, RPM_MISC_CLK_TYPE,

			  XO_ID, 19200000);

DEFINE_CLK_RPM_SMD_BRANCH(cxo_clk_src, cxo_clk_src_ao, RPM_MISC_CLK_TYPE,

DEFINE_CLK_RPM_SMD_BRANCH(cxo_clk_src, cxo_a_clk_src, RPM_MISC_CLK_TYPE,

			  CXO_CLK_SRC_ID, 19200000);

DEFINE_CLK_RPM_SMD_BRANCH(mss_cfg_ahb_clk, mss_cfg_ahb_a_clk, RPM_MCFG_CLK_TYPE,

			  MSS_CFG_AHB_CLK_ID, 19200000);
@@ -258,7 +258,7 @@ static struct pll_vote_clk gpll0_ao = { 
	.base = &virt_base,

	.c = {

		.rate = 600000000,

		.parent = &xo_ao.c,

		.parent = &xo_a_clk.c,

		.dbg_name = "gpll0_ao",

		.ops = &clk_ops_pll_acpu_vote,

		CLK_INIT(gpll0_ao.c),
@@ -1329,9 +1329,9 @@ static struct mux_clk gcc_debug_mux = { 


static struct clk_lookup msm_clocks_rpm_californium[] = {

	CLK_LIST(xo),

	CLK_LIST(xo_ao),

	CLK_LIST(xo_a_clk),

	CLK_LIST(cxo_clk_src),

	CLK_LIST(cxo_clk_src_ao),

	CLK_LIST(cxo_a_clk_src),

	CLK_LIST(mss_cfg_ahb_clk),

	CLK_LIST(mss_cfg_ahb_a_clk),

	CLK_LIST(ce_clk),
@@ -1511,7 +1511,7 @@ static int msm_gcc_californium_probe(struct platform_device *pdev) 
	clk_set_rate(&pcnoc_keepalive_a_clk.c, 19200000);

	clk_prepare_enable(&pcnoc_keepalive_a_clk.c);



	clk_prepare_enable(&xo_ao.c);

	clk_prepare_enable(&xo_a_clk.c);



	dev_info(&pdev->dev, "Registered GCC clocks.\n");

include/dt-bindings/clock/msm-clocks-californium.h

+2 −2
Original line number Diff line number Diff line
@@ -16,9 +16,9 @@ 


/* RPM controlled clocks */

#define clk_xo 0xf13dfee3

#define clk_xo_ao 0x480207b3

#define clk_xo_a_clk 0xd939b99b

#define clk_cxo_clk_src 0x79e95308

#define clk_cxo_clk_src_ao 0x64eb6004

#define clk_cxo_a_clk_src 0x3dba80d6

#define clk_mss_cfg_ahb_clk 0x4a6d85ae

#define clk_mss_cfg_ahb_a_clk 0x2a1502ca

#define clk_ce_clk 0xd8bc64e1