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Commit c95d330d authored by Binoy Jayan's avatar Binoy Jayan
Browse files

ARM: dts: mdm: Add dt entries for MDM9640 



Make the following changes for mdm9640:
 - tlmm_pinmux entry for blsp_uart2, timer, wcd9xxx_intc
 - dt entries for pcie, spi, i2c, and sdhc

Change-Id: I89f876e6fa63f9e3dc9416145e14cb04afd13da9
Signed-off-by: default avatarBinoy Jayan <bjayan@codeaurora.org>
parent 5ab781a9

arch/arm/boot/dts/qcom/mdm9640.dtsi

+329 −2
Original line number Diff line number Diff line
@@ -28,7 +28,11 @@ 
		smd11 = &smdtty_data11;

		smd21 = &smdtty_data21;

		smd36 = &smdtty_loopback;

		spi0 = &spi_0;

		spi1 = &spi_1;

		i2c3 = &i2c_3;

		qpic_nand1 = &qnand_1;

		sdhc1 = &sdhc_1; /* SDC1 eMMC/SD slot */

	};



	reserved-memory {
@@ -131,6 +135,7 @@ 
	restart@4ab000 {

		compatible = "qcom,pshold";

		reg = <0x4ab000 0x4>;

		reg-names = "pshold-base";

	};



	timer@b020000 {
@@ -231,7 +236,8 @@ 
		#interrupt-cells = <1>;

		interrupt-map-mask = <0xffffffff>;

		interrupt-map = <0 &intc 0 108 0

				1 &intc 0 238 0>;

				1 &intc 0 238 0

				2 &tlmm_pinmux 5 0>;



		qcom,inject-rx-on-wakeup;

		qcom,rx-char-to-inject = <0xFD>;
@@ -242,6 +248,9 @@ 
		clock-names = "core_clk", "iface_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,

			<&clock_gcc clk_gcc_blsp1_ahb_clk>;

		pinctrl-names = "sleep", "default";

		pinctrl-0 = <&uart2_console_sleep>;

		pinctrl-1 = <&uart2_console_active>;



		qcom,msm-bus,name = "buart2";

		qcom,msm-bus,num-cases = <2>;
@@ -264,6 +273,70 @@ 
		qcom,pipe-attr-ee;

	};



	pcie_ep: qcom,pcie@bfffd000 {

		compatible = "qcom,pcie-ep";



		reg = <0x7fffd000 0x1000>,

			<0x7fffe000 0xf1d>,

			<0x7fffef20 0xa8>,

			<0x00080000 0x2000>,

			<0x00086000 0x1000>,

			<0x00087000 0x1000>;

		reg-names = "msi", "dm_core", "elbi", "parf", "phy", "mmio";



		#address-cells = <0>;

		interrupt-parent = <&pcie_ep>;

		interrupts = <0 1 2 3 4 5>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xffffffff>;

		interrupt-map = <0 &intc 0 52 0

				1 &intc 0 54 0

				2 &intc 0 55 0

				3 &intc 0 58 0

				4 &intc 0 59 0

				5 &intc 0 60 0>;

		interrupt-names = "int_pm_turnoff", "int_dstate_change",

				"int_l1sub_timeout", "int_link_up",

				"int_link_down", "int_bridge_flush_n";



		pinctrl-names = "default";

		pinctrl-0 = <&pcie0_clkreq_default

			     &pcie0_perst_default &pcie0_wake_default>;



		perst-gpio = <&tlmm_pinmux 65 0>;

		wake-gpio = <&tlmm_pinmux 61 0>;

		clkreq-gpio = <&tlmm_pinmux 64 0>;



		gdsc-vdd-supply = <&gdsc_pcie>;

		vreg-1.8-supply = <&pmd9635_l8>;

		vreg-0.9-supply = <&pmd9635_l4>;



		clocks = <&clock_gcc clk_gcc_pcie_pipe_clk>,

			<&clock_gcc clk_gcc_pcie_cfg_ahb_clk>,

			<&clock_gcc clk_gcc_pcie_axi_mstr_clk>,

			<&clock_gcc clk_gcc_pcie_axi_clk>,

			<&clock_gcc clk_gcc_pcie_sleep_clk>,

			<&clock_gcc clk_pcie_gpio_ldo>,

			<&clock_gcc clk_gcc_pcie_phy_reset>;



		clock-names = "pcie_0_pipe_clk", "pcie_0_cfg_ahb_clk",

				"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",

				"pcie_0_aux_clk", "pcie_0_ldo",

				"pcie_0_phy_reset";

		max-clock-frequency-hz = <125000000>, <0>,

					<0>, <0>, <1000000>, <0>, <0>;



		qcom,msm-bus,name = "pcie-ep";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<45 512 0 0>,

				<45 512 500 800>;



		qcom,pcie-link-speed = <2>;

		qcom,pcie-phy-ver = <3>;

	};



	ipa_hw: qcom,ipa@07900000 {

		compatible = "qcom,ipa";

		reg = <0x07900000 0x4EFFC>,
@@ -352,6 +425,134 @@ 
                        < 1190400 >;

        };



	spi_0: spi@78b5000 { /* BLSP1 QUP1 */

		compatible = "qcom,spi-qup-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "spi_physical", "spi_bam_physical";

		reg = <0x78b5000 0x600>,

		      <0x7884000 0x23000>;

		interrupt-names = "spi_irq", "spi_bam_irq";

		interrupts = <0 95 0>, <0 238 0>;

		spi-max-frequency = <50000000>;

		pinctrl-names = "spi_default", "spi_sleep";

		pinctrl-0 = <&spi0_default &spi0_cs0_active>;

		pinctrl-1 = <&spi0_sleep &spi0_cs0_sleep>;

		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,

			 <&clock_gcc clk_gcc_blsp1_qup1_spi_apps_clk>;

		clock-names = "iface_clk", "core_clk";

		qcom,infinite-mode = <0>;

		qcom,use-pinctrl;

		qcom,ver-reg-exists;

		qcom,master-id = <86>;

		status = "disabled";

	};



	spi_1: spi@78b6000 { /* BLSP1 QUP2 */

		compatible = "qcom,spi-qup-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "spi_physical", "spi_bam_physical";

		reg = <0x78b6000 0x600>,

		      <0x7884000 0x23000>;

		interrupt-names = "spi_irq", "spi_bam_irq";

		interrupts = <0 96 0>, <0 238 0>;

		spi-max-frequency = <50000000>;

		pinctrl-names = "spi_default", "spi_sleep";

		pinctrl-0 = <&spi1_default &spi1_cs0_active>;

		pinctrl-1 = <&spi1_sleep &spi1_cs0_sleep>;

		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,

			 <&clock_gcc clk_gcc_blsp1_qup2_spi_apps_clk>;

		clock-names = "iface_clk", "core_clk";

		qcom,infinite-mode = <0>;

		qcom,use-pinctrl;

		qcom,ver-reg-exists;

		qcom,master-id = <86>;

	};



	pcie0: qcom,pcie@80000 {

		compatible = "qcom,pci-msm";

		cell-index = <0>;



		reg = <0x00080000 0x2000>,

		      <0x00086000 0x1000>,

		      <0x40000000 0xf1d>,

		      <0x40000f20 0xa8>,

		      <0x40100000 0x100000>,

		      <0x40200000 0x100000>,

		      <0x40300000 0xd00000>;



		reg-names = "parf", "phy", "dm_core", "elbi",

				"conf", "io", "bars";



		#address-cells = <0>;

		interrupt-parent = <&pcie0>;

		interrupts = <0 1 2 3 4 5 6 7 8 9 10 11>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xffffffff>;

		interrupt-map = <0 &intc 0 49 0

				1 &intc 0 50 0

				2 &intc 0 51 0

				3 &intc 0 52 0

				4 &intc 0 53 0

				5 &intc 0 54 0

				6 &intc 0 55 0

				7 &intc 0 56 0

				8 &intc 0 57 0

				9 &intc 0 58 0

				10 &intc 0 59 0

				11 &intc 0 60 0>;



		interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d",

				"int_pls_pme", "int_pme_legacy", "int_pls_err",

				"int_aer_legacy", "int_pls_link_up",

				"int_pls_link_down", "int_bridge_flush_n";



		pinctrl-names = "default";

		pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default

			     &pcie0_wake_default>;



		perst-gpio = <&tlmm_pinmux 61 0>;

		wake-gpio = <&tlmm_pinmux 65 0>;



		gdsc-vdd-supply = <&gdsc_pcie>;

		vreg-1.8-supply = <&pmd9635_l8>;

		vreg-0.9-supply = <&pmd9635_l4>;



		qcom,l1-supported;

		qcom,l1ss-supported;

		qcom,aux-clk-sync;



		qcom,ep-wakeirq;



		qcom,ep-latency = <10>;



		qcom,msm-bus,name = "pcie0";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<45 512 0 0>,

				<45 512 500 800>;



		clocks = <&clock_gcc clk_gcc_pcie_pipe_clk>,

			<&clock_gcc clk_ln_bb_clk>,

			<&clock_gcc clk_gcc_pcie_sleep_clk>,

			<&clock_gcc clk_gcc_pcie_cfg_ahb_clk>,

			<&clock_gcc clk_gcc_pcie_axi_mstr_clk>,

			<&clock_gcc clk_gcc_pcie_axi_clk>,

			<&clock_gcc clk_pcie_gpio_ldo>,

			<&clock_gcc clk_gcc_pcie_phy_reset>;



		clock-names =  "pcie_0_pipe_clk", "pcie_0_ref_clk_src",

			"pcie_0_aux_clk",

			"pcie_0_cfg_ahb_clk", "pcie_0_mstr_axi_clk",

			"pcie_0_slv_axi_clk", "pcie_0_ldo",

			"pcie_0_phy_reset";



		max-clock-frequency-hz = <125000000>, <0>, <1000000>,

					 <0>, <0>, <0>, <0>, <0>, <0>;

	};



	dma_blsp1: qcom,sps-dma@7884000 { /* BLSP1 */

		#dma-cells = <4>;

		compatible = "qcom,sps-dma";
@@ -360,6 +561,102 @@ 
		qcom,summing-threshold = <10>;

	};



	i2c_3: i2c@78b7000 { /* BLSP1 QUP3 */

		compatible = "qcom,i2c-msm-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "qup_phys_addr";

		reg = <0x78b7000 0x1000>;

		interrupt-names = "qup_irq";

		interrupts = <0 97 0>;

		qcom,clk-freq-out = <400000>;

		qcom,clk-freq-in  = <19200000>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,

		<&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>;

		pinctrl-names = "i2c_active", "i2c_sleep";

		pinctrl-0 = <&i2c_3_active>;

		pinctrl-1 = <&i2c_3_sleep>;

		qcom,noise-rjct-scl = <0>;

		qcom,noise-rjct-sda = <0>;

		dmas = <&dma_blsp1 12 64 0x20000020 0x20>,

			<&dma_blsp1 13 32 0x20000020 0x20>;

			dma-names = "tx", "rx";

		qcom,master-id = <86>;



		wcd9xxx_codec@d{

			compatible = "qcom,wcd9xxx-i2c";

			reg = <0x0d>;

			qcom,cdc-reset-gpio = <&tlmm_pinmux 90 0>;

			interrupt-parent = <&wcd9xxx_intc>;

			interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

				      17 18 19 20 21 22 23 24 25 26 27 28 29

				      30 31>;

			cdc-vdd-buck-supply = <&codec_buck_vreg>;

			qcom,cdc-vdd-buck-voltage = <2150000 2150000>;

			qcom,cdc-vdd-buck-current = <650000>;



			cdc-vdd-tx-h-supply = <&pmd9635_l6>;

			qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>;

			qcom,cdc-vdd-tx-h-current = <25000>;



			cdc-vdd-rx-h-supply = <&pmd9635_l6>;

			qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>;

			qcom,cdc-vdd-rx-h-current = <25000>;



			cdc-vddpx-1-supply = <&pmd9635_l6>;

			qcom,cdc-vddpx-1-voltage = <1800000 1800000>;

			qcom,cdc-vddpx-1-current = <10000>;



			cdc-vdd-a-1p2v-supply = <&pmd9635_l1>;

			qcom,cdc-vdd-a-1p2v-voltage = <1225000 1225000>;

			qcom,cdc-vdd-a-1p2v-current = <20000>;



			cdc-vddcx-1-supply = <&pmd9635_l2>;

			qcom,cdc-vddcx-1-voltage = <1200000 1200000>;

			qcom,cdc-vddcx-1-current = <10000>;



			cdc-vddcx-2-supply = <&pmd9635_l2>;

			qcom,cdc-vddcx-2-voltage = <1200000 1200000>;

			qcom,cdc-vddcx-2-current = <10000>;



			qcom,cdc-static-supplies = "cdc-vdd-buck",

						   "cdc-vdd-tx-h",

						   "cdc-vdd-rx-h",

						   "cdc-vddpx-1",

						   "cdc-vdd-a-1p2v",

						   "cdc-vddcx-1",

						   "cdc-vddcx-2";



			qcom,cdc-micbias-ldoh-v = <0x3>;

			qcom,cdc-micbias-cfilt1-mv = <1800>;

			qcom,cdc-micbias-cfilt2-mv = <2700>;

			qcom,cdc-micbias-cfilt3-mv = <1800>;

			qcom,cdc-micbias1-cfilt-sel = <0x0>;

			qcom,cdc-micbias2-cfilt-sel = <0x1>;

			qcom,cdc-micbias3-cfilt-sel = <0x2>;

			qcom,cdc-micbias4-cfilt-sel = <0x2>;

			qcom,cdc-mclk-clk-rate = <12288000>;

			qcom,cdc-dmic-sample-rate = <4800000>;

			qcom,cdc-variant = "WCD9330";

		};



		wcd9xxx_codec@77{

			compatible = "qcom,wcd9xxx-i2c";

			reg = <0x77>;

		};



		wcd9xxx_codec@66{

			compatible = "qcom,wcd9xxx-i2c";

			reg = <0x66>;

		};



		wcd9xxx_codec@55{

			compatible = "qcom,wcd9xxx-i2c";

			reg = <0x55>;

		};

	};



	spmi_bus: qcom,spmi@200f000 {

		compatible = "qcom,spmi-pmic-arb";

		reg = <0x200f000 0x1000>,
@@ -615,6 +912,35 @@ 
		status = "disabled";

	};



	sdhc_1: sdhci@7824000 {

		compatible = "qcom,sdhci-msm";

		reg = <0x07824900 0x11c>, <0x07824000 0x800>;

		reg-names = "hc_mem", "core_mem";



		interrupts = <0 123 0>, <0 138 0>;

		interrupt-names = "hc_irq", "pwr_irq";



		qcom,cpu-dma-latency-us = <701>;

		qcom,msm-bus,name = "sdhc1";

		qcom,msm-bus,num-cases = <8>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */

				<78 512 1600 3200>,    /* 400 KB/s*/

				<78 512 80000 160000>, /* 20 MB/s */

				<78 512 100000 200000>, /* 25 MB/s */

				<78 512 200000 400000>, /* 50 MB/s */

				<78 512 400000 800000>, /* 100 MB/s */

				<78 512 400000 800000>, /* 200 MB/s */

				<78 512 2048000 4096000>; /* Max. bandwidth */

		qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000

						100000000 200000000 4294967295>;

		clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>,

			 <&clock_gcc clk_gcc_sdcc1_apps_clk>;

		clock-names = "iface_clk", "core_clk";



		status = "disabled";

	};



	usb3: ssusb@8a00000{

		compatible = "qcom,dwc-usb3-msm";

		reg = <0x08a00000 0xfc000>,
@@ -863,7 +1189,8 @@ 
		compatible = "qcom,wcd9xxx-irq";

		interrupt-controller;

		#interrupt-cells = <1>;

		interrupts = <94 0>;

		interrupt-parent = <&tlmm_pinmux>;

		qcom,gpio-connect = <&tlmm_pinmux 94 0>;

		interrupt-names = "cdc-int";

	};