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Commit c91321e8 authored by Olof Johansson's avatar Olof Johansson
Browse files

ARM: arm-soc: Merge branch 'next/smp' into next/soc2



Merging in the smp-on-socfpga branch into soc2 since the topics are similar
and it's a short branch in the first place.

* next/smp:
  ARM: socfpga: mark secondary_trampoline as cpuinit
  socfpga: map uart into virtual address space so that early_printk() works
  ARM: socfpga: fix build break for allyesconfig
  ARM: socfpga: Enable SMP for socfpga

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 1f1ba836 9560f840
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+11 −0
Original line number Diff line number Diff line
Altera SOCFPGA Reset Manager

Required properties:
- compatible : "altr,rst-mgr"
- reg : Should contain 1 register ranges(address and length)

Example:
	 rstmgr@ffd05000 {
		compatible = "altr,rst-mgr";
		reg = <0xffd05000 0x1000>;
	};
+11 −0
Original line number Diff line number Diff line
Altera SOCFPGA System Manager

Required properties:
- compatible : "altr,sys-mgr"
- reg : Should contain 1 register ranges(address and length)

Example:
	 sysmgr@ffd08000 {
		compatible = "altr,sys-mgr";
		reg = <0xffd08000 0x1000>;
	};
+10 −0
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@@ -143,5 +143,15 @@
			reg-shift = <2>;
			reg-io-width = <4>;
		};

		rstmgr@ffd05000 {
				compatible = "altr,rst-mgr";
				reg = <0xffd05000 0x1000>;
			};

		sysmgr@ffd08000 {
				compatible = "altr,sys-mgr";
				reg = <0xffd08000 0x4000>;
			};
	};
};
+2 −1
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@@ -18,9 +18,10 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_MACH_SOCFPGA_CYCLONE5=y
CONFIG_ARM_THUMBEE=y
# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
# CONFIG_CACHE_L2X0 is not set
CONFIG_HIGH_RES_TIMERS=y
CONFIG_VMSPLIT_2G=y
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
+1 −0
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@@ -12,5 +12,6 @@ config ARCH_SOCFPGA
	select GENERIC_CLOCKEVENTS
	select GPIO_PL061 if GPIOLIB
	select HAVE_ARM_SCU
	select HAVE_SMP
	select SPARSE_IRQ
	select USE_OF
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