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Commit c9018aab authored by Vincent Guittot's avatar Vincent Guittot Committed by Russell King
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ARM: 7011/1: Add ARM cpu topology definition 



The affinity between ARM processors is defined in the MPIDR register.
We can identify which processors are in the same cluster,
and which ones have performance interdependency. We can define the
cpu topology of ARM platform, that is then used by sched_mc and sched_smt.

The default state of sched_mc and sched_smt config is disable.
When enabled, the behavior of the scheduler can be modified with
sched_mc_power_savings and sched_smt_power_savings sysfs interfaces.

Changes since v4 :
*  Remove unnecessary parentheses and blank lines

Changes since v3 :
* Update the format of printk message
* Remove blank line

Changes since v2 :
* Update the commit message and some comments

Changes since v1 :
* Update the commit message
* Add read_cpuid_mpidr in arch/arm/include/asm/cputype.h
* Modify header of arch/arm/kernel/topology.c
* Modify tests and manipulation of MPIDR's bitfields
* Modify the place and dependancy of the config
* Modify Noop functions

Signed-off-by: default avatarVincent Guittot <vincent.guittot@linaro.org>
Reviewed-by: default avatarAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent d0a77454

arch/arm/Kconfig

+25 −0
Original line number Diff line number Diff line
@@ -1393,6 +1393,31 @@ config SMP_ON_UP 


	  If you don't know what to do here, say Y.



config ARM_CPU_TOPOLOGY

	bool "Support cpu topology definition"

	depends on SMP && CPU_V7

	default y

	help

	  Support ARM cpu topology definition. The MPIDR register defines

	  affinity between processors which is then used to describe the cpu

	  topology of an ARM System.



config SCHED_MC

	bool "Multi-core scheduler support"

	depends on ARM_CPU_TOPOLOGY

	help

	  Multi-core scheduler support improves the CPU scheduler's decision

	  making when dealing with multi-core CPU chips at a cost of slightly

	  increased overhead in some places. If unsure say N here.



config SCHED_SMT

	bool "SMT scheduler support"

	depends on ARM_CPU_TOPOLOGY

	help

	  Improves the CPU scheduler's decision making when dealing with

	  MultiThreading at a cost of slightly increased overhead in some

	  places. If unsure say N here.



config HAVE_ARM_SCU

	bool

	help

arch/arm/include/asm/cputype.h

+6 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#define CPUID_CACHETYPE	1

#define CPUID_TCM	2

#define CPUID_TLBTYPE	3

#define CPUID_MPIDR	5



#define CPUID_EXT_PFR0	"c1, 0"

#define CPUID_EXT_PFR1	"c1, 1"
@@ -70,6 +71,11 @@ static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void) 
	return read_cpuid(CPUID_TCM);

}



static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)

{

	return read_cpuid(CPUID_MPIDR);

}



/*

 * Intel's XScale3 core supports some v6 features (supersections, L2)

 * but advertises itself as v5 as it does not support the v6 ISA.  For

arch/arm/include/asm/topology.h

+33 −0
Original line number Diff line number Diff line 
#ifndef _ASM_ARM_TOPOLOGY_H

#define _ASM_ARM_TOPOLOGY_H



#ifdef CONFIG_ARM_CPU_TOPOLOGY



#include <linux/cpumask.h>



struct cputopo_arm {

	int thread_id;

	int core_id;

	int socket_id;

	cpumask_t thread_sibling;

	cpumask_t core_sibling;

};



extern struct cputopo_arm cpu_topology[NR_CPUS];



#define topology_physical_package_id(cpu)	(cpu_topology[cpu].socket_id)

#define topology_core_id(cpu)		(cpu_topology[cpu].core_id)

#define topology_core_cpumask(cpu)	(&cpu_topology[cpu].core_sibling)

#define topology_thread_cpumask(cpu)	(&cpu_topology[cpu].thread_sibling)



#define mc_capable()	(cpu_topology[0].socket_id != -1)

#define smt_capable()	(cpu_topology[0].thread_id != -1)



void init_cpu_topology(void);

void store_cpu_topology(unsigned int cpuid);

const struct cpumask *cpu_coregroup_mask(unsigned int cpu);



#else



static inline void init_cpu_topology(void) { }

static inline void store_cpu_topology(unsigned int cpuid) { }



#endif



#include <asm-generic/topology.h>



#endif /* _ASM_ARM_TOPOLOGY_H */

arch/arm/kernel/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -66,6 +66,7 @@ obj-$(CONFIG_IWMMXT) += iwmmxt.o 
obj-$(CONFIG_CPU_HAS_PMU)	+= pmu.o

obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event.o

AFLAGS_iwmmxt.o			:= -Wa,-mcpu=iwmmxt

obj-$(CONFIG_ARM_CPU_TOPOLOGY)  += topology.o



ifneq ($(CONFIG_ARCH_EBSA110),y)

  obj-y		+= io.o

arch/arm/kernel/smp.c

+5 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
#include <asm/cacheflush.h>

#include <asm/cpu.h>

#include <asm/cputype.h>

#include <asm/topology.h>

#include <asm/mmu_context.h>

#include <asm/pgtable.h>

#include <asm/pgalloc.h>
@@ -268,6 +269,8 @@ static void __cpuinit smp_store_cpu_info(unsigned int cpuid) 
	struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid);



	cpu_info->loops_per_jiffy = loops_per_jiffy;



	store_cpu_topology(cpuid);

}



/*
@@ -358,6 +361,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus) 
{

	unsigned int ncores = num_possible_cpus();



	init_cpu_topology();



	smp_store_cpu_info(smp_processor_id());



	/*