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Commit c8eef65a authored by Charulatha V's avatar Charulatha V Committed by Tarun Kanti DebBarma
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gpio/omap: avoid cpu checks during module ena/disable 



Remove cpu-is checks while enabling/disabling OMAP GPIO module during a gpio
request/free.

Signed-off-by: default avatarCharulatha V <charu@ti.com>
Reviewed-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: default avatarTony Lindgren <tony@atomide.com>
Reviewed-by: default avatarKevin Hilman <khilman@ti.com>
Signed-off-by: default avatarKevin Hilman <khilman@ti.com>
parent 803a2434

arch/arm/mach-omap2/gpio.c

+2 −0
Original line number Diff line number Diff line
@@ -88,6 +88,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) 
		pdata->regs->clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1;

		pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL;

		pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN;

		pdata->regs->ctrl = OMAP24XX_GPIO_CTRL;

		break;

	case 2:

		pdata->bank_type = METHOD_GPIO_44XX;
@@ -104,6 +105,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) 
		pdata->regs->clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0;

		pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME;

		pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE;

		pdata->regs->ctrl = OMAP4_GPIO_CTRL;

		break;

	default:

		WARN(1, "Invalid gpio bank_type\n");

arch/arm/plat-omap/include/plat/gpio.h

+1 −0
Original line number Diff line number Diff line
@@ -188,6 +188,7 @@ struct omap_gpio_reg_offs { 
	u16 clr_irqenable;

	u16 debounce;

	u16 debounce_en;

	u16 ctrl;



	bool irqenable_inv;

};

drivers/gpio/gpio-omap.c

+23 −30
Original line number Diff line number Diff line
@@ -83,6 +83,7 @@ struct gpio_bank { 


#define GPIO_INDEX(bank, gpio) (gpio % bank->width)

#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))

#define GPIO_MOD_CTRL_BIT	BIT(0)



static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)

{
@@ -577,22 +578,18 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) 
		__raw_writel(__raw_readl(reg) | (1 << offset), reg);

	}

#endif

	if (!cpu_class_is_omap1()) {

		if (!bank->mod_usage) {

			void __iomem *reg = bank->base;

	if (bank->regs->ctrl && !bank->mod_usage) {

		void __iomem *reg = bank->base + bank->regs->ctrl;

		u32 ctrl;



			if (cpu_is_omap24xx() || cpu_is_omap34xx())

				reg += OMAP24XX_GPIO_CTRL;

			else if (cpu_is_omap44xx())

				reg += OMAP4_GPIO_CTRL;

		ctrl = __raw_readl(reg);

		/* Module is enabled, clocks are not gated */

			ctrl &= 0xFFFFFFFE;

		ctrl &= ~GPIO_MOD_CTRL_BIT;

		__raw_writel(ctrl, reg);

	}



	bank->mod_usage |= 1 << offset;

	}



	spin_unlock_irqrestore(&bank->lock, flags);



	return 0;
@@ -625,22 +622,18 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) 
		__raw_writel(1 << offset, reg);

	}

#endif

	if (!cpu_class_is_omap1()) {

	bank->mod_usage &= ~(1 << offset);

		if (!bank->mod_usage) {

			void __iomem *reg = bank->base;



	if (bank->regs->ctrl && !bank->mod_usage) {

		void __iomem *reg = bank->base + bank->regs->ctrl;

		u32 ctrl;



			if (cpu_is_omap24xx() || cpu_is_omap34xx())

				reg += OMAP24XX_GPIO_CTRL;

			else if (cpu_is_omap44xx())

				reg += OMAP4_GPIO_CTRL;

		ctrl = __raw_readl(reg);

		/* Module is disabled, clocks are gated */

			ctrl |= 1;

		ctrl |= GPIO_MOD_CTRL_BIT;

		__raw_writel(ctrl, reg);

	}

	}



	_reset_gpio(bank, bank->chip.base + offset);

	spin_unlock_irqrestore(&bank->lock, flags);

}