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Commit c8af34b4 authored by Ezequiel Garcia's avatar Ezequiel Garcia Committed by Daniel Lezcano
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clocksource: armada-370-xp: Use atomic access for shared registers 



Replace the driver-specific thread-safe shared register API
by the recently introduced atomic_io_clear_set().

Signed-off-by: default avatarEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
parent 0a54a069

drivers/clocksource/time-armada-370-xp.c

+4 −8
Original line number Diff line number Diff line
@@ -85,12 +85,6 @@ static u32 ticks_per_jiffy; 


static struct clock_event_device __percpu *armada_370_xp_evt;



static void timer_ctrl_clrset(u32 clr, u32 set)

{

	writel((readl(timer_base + TIMER_CTRL_OFF) & ~clr) | set,

		timer_base + TIMER_CTRL_OFF);

}



static void local_timer_ctrl_clrset(u32 clr, u32 set)

{

	writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set,
@@ -245,7 +239,7 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np) 
		clr = TIMER0_25MHZ;

		enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);

	}

	timer_ctrl_clrset(clr, set);

	atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set);

	local_timer_ctrl_clrset(clr, set);



	/*
@@ -263,7 +257,9 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np) 
	writel(0xffffffff, timer_base + TIMER0_VAL_OFF);

	writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);



	timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);

	atomic_io_modify(timer_base + TIMER_CTRL_OFF,

		TIMER0_RELOAD_EN | enable_mask,

		TIMER0_RELOAD_EN | enable_mask);



	/*

	 * Set scale and timer for sched_clock.