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Commit c859fa04 authored by Prasad Sodagudi's avatar Prasad Sodagudi
Browse files

ARM: dts: msm: Add support for MSMTITANIUM 



Add initial set of device tree and board files to build
the msmtitanium target.

Change-Id: I23281a8dbfe60701545254e18154433a2fc1cc90
Signed-off-by: default avatarPrasad Sodagudi <psodagud@codeaurora.org>
parent e0110676

Documentation/devicetree/bindings/arm/msm/msm.txt

+5 −0
Original line number Diff line number Diff line
@@ -80,6 +80,9 @@ SoCs: 
- APQ8052

  compatible = "qcom,apq8052"



- MSMTITANIUM

  compatible = "qcom,msmtitanium"



- MSMZIRC

  compatible = "qcom,msmzirc"
@@ -209,6 +212,8 @@ compatible = "qcom,msm8952-cdp" 
compatible = "qcom,msm8952-mtp"

compatible = "qcom,apq8052-cdp"

compatible = "qcom,apq8052-mtp"

compatible = "qcom,msmtitanium-rumi"

compatible = "qcom,msmtitanium-sim"

compatible = "qcom,msmzirc-cdp"

compatible = "qcom,msmzirc-mtp"

compatible = "qcom,msmzirc-rumi"

arch/arm/boot/dts/qcom/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -50,6 +50,9 @@ dtb-$(CONFIG_ARCH_MDM9640) += mdm9640-sim.dtb \ 
	mdm9640-nand-cdp.dtb \

	mdm9640-mtp.dtb



dtb-$(CONFIG_ARCH_MSMTITANIUM) += msmtitanium-sim.dtb \

	msmtitanium-rumi.dtb



targets += dtbs

targets += $(addprefix ../, $(dtb-y))

endif

arch/arm/boot/dts/qcom/msmtitanium-cpu.dtsi

0 → 100644
+192 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



/ {

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		cpu-map {

			cluster0 {

				core0 {

					cpu = <&CPU0>;

				};

				core1 {

					cpu = <&CPU1>;

				};

				core2 {

					cpu = <&CPU2>;

				};

				core3 {

					cpu = <&CPU3>;

				};

			};



			cluster1 {

				core0 {

					cpu = <&CPU4>;

				};

				core1 {

					cpu = <&CPU5>;

				};

				core2 {

					cpu = <&CPU6>;

				};

				core3 {

					cpu = <&CPU7>;

				};

			};

		};



		CPU0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x46000000>;

			qcom,acc = <&acc0>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      power-domain = <&l2ccc_0>;

			};

		};



		CPU1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x1>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x46000000>;

			qcom,acc = <&acc1>;

			next-level-cache = <&L2_0>;

		};



		CPU2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x2>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x46000000>;

			qcom,acc = <&acc2>;

			next-level-cache = <&L2_0>;

		};



		CPU3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x3>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x46000000>;

			qcom,acc = <&acc3>;

			next-level-cache = <&L2_0>;

		};



		CPU4: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x100>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x46000000>;

			qcom,acc = <&acc4>;

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      power-domain = <&l2ccc_1>;

			};

		};



		CPU5: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x101>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x46000000>;

			qcom,acc = <&acc5>;

			next-level-cache = <&L2_1>;

		};



		CPU6: cpu@102 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x102>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x46000000>;

			qcom,acc = <&acc6>;

			next-level-cache = <&L2_1>;

		};



		CPU7: cpu@103 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x103>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x46000000>;

			qcom,acc = <&acc7>;

			next-level-cache = <&L2_1>;

		};

	};

};



&soc {

	l2ccc_0: clock-controller@b111000 {

		compatible = "qcom,8916-l2ccc";

		reg = <0x0b111000 0x1000>;

	};



	l2ccc_1: clock-controller@b011000 {

		compatible = "qcom,8916-l2ccc";

		reg = <0x0b011000 0x1000>;

	};



	acc0:clock-controller@b088000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b088000 0x1000>;

	};



	acc1:clock-controller@b098000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b098000 0x1000>;

	};



	acc2:clock-controller@b0a8000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b0a8000 0x1000>;

	};



	acc3:clock-controller@b0b8000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b0b8000 0x1000>;

	};



	acc4:clock-controller@b188000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b188000 0x1000>;

	};



	acc5:clock-controller@b198000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b198000 0x1000>;

	};



	acc6:clock-controller@b1a8000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b1a8000 0x1000>;

	};



	acc7:clock-controller@b1b8000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b1b8000 0x1000>;

	};

};

arch/arm/boot/dts/qcom/msmtitanium-pinctrl.dtsi

0 → 100644
+54 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&soc {

	tlmm: pinctrl@1000000 {

		compatible = "qcom,msmtitanium-pinctrl";

		reg = <0x1000000 0x300000>;

		interrupts = <0 208 0>;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;



		pmx-uartconsole {

			uart_console_active: uart_console_active {

				mux {

					pins = "gpio4", "gpio5";

					function = "blsp_uart2";

				};



				config {

					pins = "gpio4", "gpio5";

					drive-strength = <2>;

					bias-disable;

				};

			};



			uart_console_sleep: uart_console_sleep {

				mux {

					pins = "gpio4", "gpio5";

					function = "blsp_uart2";

				};



				config {

					pins = "gpio4", "gpio5";

					drive-strength = <2>;

					bias-pull-down;

				};

			};



		};



	};

};

arch/arm/boot/dts/qcom/msmtitanium-rumi.dts

0 → 100644
+30 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



/dts-v1/;



/memreserve/ 0x46000000 0x00000200;



#include "msmtitanium.dtsi"



/ {

	model = "Qualcomm Technologies, Inc. MSMTitanium RUMI";

	compatible = "qcom,msmtitanium-rumi", "qcom,msmtitanium", "qcom,rumi";

	qcom,board-id= <15 0>;

};



&soc {

	timer {

		clock-frequency = <10000000>;

	};

};