Loading arch/mips/au1000/common/setup.c +1 −5 Original line number Diff line number Diff line Loading @@ -57,7 +57,7 @@ extern void au1xxx_time_init(void); extern void au1xxx_timer_setup(struct irqaction *irq); extern void set_cpuspec(void); static int __init au1x00_setup(void) void __init plat_setup(void) { struct cpu_spec *sp; char *argptr; Loading Loading @@ -153,12 +153,8 @@ static int __init au1x00_setup(void) au_sync(); while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S); au_writel(0, SYS_TOYTRIM); return 0; } early_initcall(au1x00_setup); #if defined(CONFIG_64BIT_PHYS_ADDR) /* This routine should be valid for all Au1x based boards */ phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) Loading arch/mips/cobalt/setup.c +1 −3 Original line number Diff line number Diff line Loading @@ -89,7 +89,7 @@ static struct pci_controller cobalt_pci_controller = { .io_offset = 0x00001000UL - GT64111_IO_BASE }; static void __init cobalt_setup(void) void __init plat_setup(void) { unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0); int i; Loading Loading @@ -125,8 +125,6 @@ static void __init cobalt_setup(void) #endif } early_initcall(cobalt_setup); /* * Prom init. We read our one and only communication with the firmware. * Grab the amount of installed memory Loading arch/mips/ddb5xxx/ddb5074/setup.c +1 −3 Original line number Diff line number Diff line Loading @@ -85,7 +85,7 @@ static void __init ddb_time_init(void) static void __init ddb5074_setup(void) void __init plat_setup(void) { set_io_port_base(NILE4_PCI_IO_BASE); isa_slot_offset = NILE4_PCI_MEM_BASE; Loading @@ -106,8 +106,6 @@ static void __init ddb5074_setup(void) panic_timeout = 180; } early_initcall(ddb5074_setup); #define USE_NILE4_SERIAL 0 #if USE_NILE4_SERIAL Loading arch/mips/ddb5xxx/ddb5476/setup.c +1 −3 Original line number Diff line number Diff line Loading @@ -124,7 +124,7 @@ static struct { static void ddb5476_board_init(void); static void __init ddb5476_setup(void) void __init plat_setup(void) { set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE)); Loading Loading @@ -158,8 +158,6 @@ static void __init ddb5476_setup(void) ddb5476_board_init(); } early_initcall(ddb5476_setup); /* * We don't trust bios. We essentially does hardware re-initialization * as complete as possible, as far as we know we can safely do. Loading arch/mips/ddb5xxx/ddb5477/setup.c +1 −5 Original line number Diff line number Diff line Loading @@ -170,7 +170,7 @@ static void ddb5477_board_init(void); extern struct pci_controller ddb5477_ext_controller; extern struct pci_controller ddb5477_io_controller; static int ddb5477_setup(void) void __init plat_setup(void) { /* initialize board - we don't trust the loader */ ddb5477_board_init(); Loading @@ -193,12 +193,8 @@ static int ddb5477_setup(void) register_pci_controller (&ddb5477_ext_controller); register_pci_controller (&ddb5477_io_controller); return 0; } early_initcall(ddb5477_setup); static void __init ddb5477_board_init(void) { /* ----------- setup PDARs ------------ */ Loading Loading
arch/mips/au1000/common/setup.c +1 −5 Original line number Diff line number Diff line Loading @@ -57,7 +57,7 @@ extern void au1xxx_time_init(void); extern void au1xxx_timer_setup(struct irqaction *irq); extern void set_cpuspec(void); static int __init au1x00_setup(void) void __init plat_setup(void) { struct cpu_spec *sp; char *argptr; Loading Loading @@ -153,12 +153,8 @@ static int __init au1x00_setup(void) au_sync(); while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S); au_writel(0, SYS_TOYTRIM); return 0; } early_initcall(au1x00_setup); #if defined(CONFIG_64BIT_PHYS_ADDR) /* This routine should be valid for all Au1x based boards */ phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) Loading
arch/mips/cobalt/setup.c +1 −3 Original line number Diff line number Diff line Loading @@ -89,7 +89,7 @@ static struct pci_controller cobalt_pci_controller = { .io_offset = 0x00001000UL - GT64111_IO_BASE }; static void __init cobalt_setup(void) void __init plat_setup(void) { unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0); int i; Loading Loading @@ -125,8 +125,6 @@ static void __init cobalt_setup(void) #endif } early_initcall(cobalt_setup); /* * Prom init. We read our one and only communication with the firmware. * Grab the amount of installed memory Loading
arch/mips/ddb5xxx/ddb5074/setup.c +1 −3 Original line number Diff line number Diff line Loading @@ -85,7 +85,7 @@ static void __init ddb_time_init(void) static void __init ddb5074_setup(void) void __init plat_setup(void) { set_io_port_base(NILE4_PCI_IO_BASE); isa_slot_offset = NILE4_PCI_MEM_BASE; Loading @@ -106,8 +106,6 @@ static void __init ddb5074_setup(void) panic_timeout = 180; } early_initcall(ddb5074_setup); #define USE_NILE4_SERIAL 0 #if USE_NILE4_SERIAL Loading
arch/mips/ddb5xxx/ddb5476/setup.c +1 −3 Original line number Diff line number Diff line Loading @@ -124,7 +124,7 @@ static struct { static void ddb5476_board_init(void); static void __init ddb5476_setup(void) void __init plat_setup(void) { set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE)); Loading Loading @@ -158,8 +158,6 @@ static void __init ddb5476_setup(void) ddb5476_board_init(); } early_initcall(ddb5476_setup); /* * We don't trust bios. We essentially does hardware re-initialization * as complete as possible, as far as we know we can safely do. Loading
arch/mips/ddb5xxx/ddb5477/setup.c +1 −5 Original line number Diff line number Diff line Loading @@ -170,7 +170,7 @@ static void ddb5477_board_init(void); extern struct pci_controller ddb5477_ext_controller; extern struct pci_controller ddb5477_io_controller; static int ddb5477_setup(void) void __init plat_setup(void) { /* initialize board - we don't trust the loader */ ddb5477_board_init(); Loading @@ -193,12 +193,8 @@ static int ddb5477_setup(void) register_pci_controller (&ddb5477_ext_controller); register_pci_controller (&ddb5477_io_controller); return 0; } early_initcall(ddb5477_setup); static void __init ddb5477_board_init(void) { /* ----------- setup PDARs ------------ */ Loading