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Commit c836b771 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] Fix EV64120 and Ocelot builds by providing a plat_timer_setup().
  [MIPS] EV64120: Fix PCI interrupt allocation.
  [MIPS] Make irq number allocator generally available for fixing EV64120.
  [MIPS] EV64120: Fix timer initialization for HZ != 100.
  [MIPS] Ocelot 3: Fix MAC address detection after platform_device conversion.
  [MIPS] Ocelot C: Fix MAC address detection after platform_device conversion.
  [MIPS] SB1: On bootup only flush cache on local CPU.
  [MIPS] Ocelot 3: Fix large number of warnings.
  [MIPS] Ocelot C: Fix mapping of ioport address range.
  [MIPS] Ocelot C: Fix warning about missmatching format string.
  [MIPS] Ocelot C: fix eth registration after conversion to platform_device
  [MIPS] Ocelot C: Fix large number of warnings.
parents 846cf85e 73f4388a

arch/mips/gt64120/common/time.c

+2 −2
Original line number Diff line number Diff line
@@ -64,14 +64,14 @@ static irqreturn_t gt64120_irq(int irq, void *dev_id) 
 * as *irq (=irq0 in ../kernel/time.c).  We will do our own timer interrupt

 * handling.

 */

void gt64120_time_init(void)

void __init plat_timer_setup(struct irqaction *irq)

{

	static struct irqaction timer;



	/* Disable timer first */

	GT_WRITE(GT_TC_CONTROL_OFS, 0);

	/* Load timer value for 100 Hz */

	GT_WRITE(GT_TC3_OFS, Sys_clock / 100);

	GT_WRITE(GT_TC3_OFS, Sys_clock / HZ);



	/*

	 * Create the IRQ structure entry for the timer.  Since we're too early

arch/mips/gt64120/ev64120/setup.c

+0 −2
Original line number Diff line number Diff line
@@ -68,7 +68,6 @@ unsigned long __init prom_free_prom_memory(void) 
 * Initializes basic routines and structures pointers, memory size (as

 * given by the bios and saves the command line.

 */

extern void gt64120_time_init(void);



void __init plat_mem_setup(void)

{
@@ -76,7 +75,6 @@ void __init plat_mem_setup(void) 
	_machine_halt = galileo_machine_halt;

	pm_power_off = galileo_machine_power_off;



	board_time_init = gt64120_time_init;

	set_io_port_base(KSEG1);

}

arch/mips/gt64120/momenco_ocelot/setup.c

+0 −3
Original line number Diff line number Diff line
@@ -70,7 +70,6 @@ extern void momenco_ocelot_restart(char *command); 
extern void momenco_ocelot_halt(void);

extern void momenco_ocelot_power_off(void);



extern void gt64120_time_init(void);

extern void momenco_ocelot_irq_setup(void);



static char reset_reason;
@@ -156,8 +155,6 @@ void __init plat_mem_setup(void) 
	void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);

	unsigned int tmpword;



	board_time_init = gt64120_time_init;



	_machine_restart = momenco_ocelot_restart;

	_machine_halt = momenco_ocelot_halt;

	pm_power_off = momenco_ocelot_power_off;

arch/mips/kernel/irq.c

+42 −0
Original line number Diff line number Diff line
@@ -26,6 +26,48 @@ 
#include <asm/system.h>

#include <asm/uaccess.h>



static unsigned long irq_map[NR_IRQS / BITS_PER_LONG];



int __devinit allocate_irqno(void)

{

	int irq;



again:

	irq = find_first_zero_bit(irq_map, NR_IRQS);



	if (irq >= NR_IRQS)

		return -ENOSPC;



	if (test_and_set_bit(irq, irq_map))

		goto again;



	return irq;

}



EXPORT_SYMBOL_GPL(allocate_irqno);



/*

 * Allocate the 16 legacy interrupts for i8259 devices.  This happens early

 * in the kernel initialization so treating allocation failure as BUG() is

 * ok.

 */

void __init alloc_legacy_irqno(void)

{

	int i;



	for (i = 0; i <= 16; i++)

		BUG_ON(test_and_set_bit(i, irq_map));

}



void __devinit free_irqno(unsigned int irq)

{

	smp_mb__before_clear_bit();

	clear_bit(irq, irq_map);

	smp_mb__after_clear_bit();

}



EXPORT_SYMBOL_GPL(free_irqno);



/*

 * 'what should we do if we get a hw irq event on an illegal vector'.

 * each architecture has to answer this themselves.

arch/mips/mm/c-sb1.c

+1 −1
Original line number Diff line number Diff line
@@ -505,5 +505,5 @@ void sb1_cache_init(void) 
	:

	: "memory");



	flush_cache_all();

	local_sb1___flush_cache_all();

}