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Commit c8102fd8 authored by Krishna Chaitanya Devarakonda's avatar Krishna Chaitanya Devarakonda Committed by Gerrit - the friendly Code Review server
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msm: clk: add support for DSI pll on MSM8937 



Add support for DSI pll in clock driver for
msm8937 target.

Change-Id: I19b0b1af8e8bdd71f1bb9e5a91e9c36c60a69b7a
Signed-off-by: default avatarKrishna Chaitanya Devarakonda <kdevarak@codeaurora.org>
parent ecbae929

drivers/clk/msm/mdss/mdss-dsi-pll-28lpm.c

+2 −1
Original line number Diff line number Diff line
@@ -363,7 +363,8 @@ int dsi_pll_clock_register_lpm(struct platform_device *pdev, 
	byte_mux_clk_ops = clk_ops_gen_mux;

	byte_mux_clk_ops.prepare = dsi_pll_mux_prepare;



	if (pll_res->target_id == MDSS_PLL_TARGET_8952) {

	if ((pll_res->target_id == MDSS_PLL_TARGET_8952) ||

		(pll_res->target_id == MDSS_PLL_TARGET_8937)) {

		rc = of_msm_clock_register(pdev->dev.of_node,

			mdss_dsi_pllcc_8916, ARRAY_SIZE(mdss_dsi_pllcc_8916));

		if (rc) {

drivers/clk/msm/mdss/mdss-pll.c

+4 −0
Original line number Diff line number Diff line
@@ -129,6 +129,9 @@ static int mdss_pll_resource_parse(struct platform_device *pdev, 
	if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8952")) {

		pll_res->pll_interface_type = MDSS_DSI_PLL_LPM;

		pll_res->target_id = MDSS_PLL_TARGET_8952;

	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8937")) {

		pll_res->pll_interface_type = MDSS_DSI_PLL_LPM;

		pll_res->target_id = MDSS_PLL_TARGET_8937;

	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8996")) {

		pll_res->pll_interface_type = MDSS_DSI_PLL_8996;

		pll_res->target_id = MDSS_PLL_TARGET_8996;
@@ -372,6 +375,7 @@ static const struct of_device_id mdss_pll_dt_match[] = { 
	{.compatible = "qcom,mdss_hdmi_pll_8996_v2"},

	{.compatible = "qcom,mdss_hdmi_pll_8996_v3"},

	{.compatible = "qcom,mdss_dsi_pll_8952"},

	{.compatible = "qcom,mdss_dsi_pll_8937"},

	{}

};

drivers/clk/msm/mdss/mdss-pll.h

+1 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ enum { 
enum {

	MDSS_PLL_TARGET_8996,

	MDSS_PLL_TARGET_8952,

	MDSS_PLL_TARGET_8937,

};



#define DFPS_MAX_NUM_OF_FRAME_RATES 10