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Commit c80a501b authored by Prasad Sodagudi's avatar Prasad Sodagudi
Browse files

ARM: dts: msm: Add L1/L2 cache dump nodes for couple of SoCs 



Add the nodes needed to define the dumping regions for the
A53 L1 instruction and data caches, as well as the A53
L2 cache. Dumping the contents of the L2 cache on the A53
clusters is not currently supported.

Change-Id: Ib49cd2f5bbce21879745430c4668cdcd3cce88d5
Signed-off-by: default avatarPrasad Sodagudi <psodagud@codeaurora.org>
parent b6a4104f

arch/arm/boot/dts/qcom/msm8917-cpu.dtsi

+76 −0
Original line number Diff line number Diff line
@@ -54,6 +54,16 @@ 
			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      power-domain = <&l2ccc_0>;

			      /* A53 L2 dump not supported */

			      qcom,dump-size = <0x0>;

			};

			L1_I_100: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};

			L1_D_100: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};

		};
@@ -66,6 +76,14 @@ 
			qcom,acc = <&acc1>;

			qcom,limits-info = <&mitigation_profile1>;

			next-level-cache = <&L2_1>;

			L1_I_101: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};

			L1_D_101: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};

		};



		CPU2: cpu@102 {
@@ -77,6 +95,14 @@ 
			qcom,acc = <&acc2>;

			qcom,limits-info = <&mitigation_profile2>;

			next-level-cache = <&L2_1>;

			L1_I_102: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};

			L1_D_102: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};

		};



		CPU3: cpu@103 {
@@ -88,6 +114,14 @@ 
			qcom,acc = <&acc3>;

			qcom,limits-info = <&mitigation_profile3>;

			next-level-cache = <&L2_1>;

			L1_I_103: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};

			L1_D_103: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};

		};



	};
@@ -118,4 +152,46 @@ 
		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b0b8000 0x1000>;

	};



	cpuss_dump {

		compatible = "qcom,cpuss-dump";

		status = "disabled";

		qcom,l2_dump1 {

			/* L2 cache dump for A53 cluster */

			qcom,dump-node = <&L2_1>;

			qcom,dump-id = <0xC1>;

		};

		qcom,l1_i_cache100 {

			qcom,dump-node = <&L1_I_100>;

			qcom,dump-id = <0x64>;

		};

		qcom,l1_i_cache101 {

			qcom,dump-node = <&L1_I_101>;

			qcom,dump-id = <0x65>;

		};

		qcom,l1_i_cache102 {

			qcom,dump-node = <&L1_I_102>;

			qcom,dump-id = <0x66>;

		};

		qcom,l1_i_cache103 {

			qcom,dump-node = <&L1_I_103>;

			qcom,dump-id = <0x67>;

		};

		qcom,l1_d_cache100 {

			qcom,dump-node = <&L1_D_100>;

			qcom,dump-id = <0x84>;

		};

		qcom,l1_d_cache101 {

			qcom,dump-node = <&L1_D_101>;

			qcom,dump-id = <0x85>;

		};

		qcom,l1_d_cache102 {

			qcom,dump-node = <&L1_D_102>;

			qcom,dump-id = <0x86>;

		};

		qcom,l1_d_cache103 {

			qcom,dump-node = <&L1_D_103>;

			qcom,dump-id = <0x87>;

		};

	};

};

arch/arm/boot/dts/qcom/msm8937-cpu.dtsi

+146 −0
Original line number Diff line number Diff line
@@ -64,6 +64,16 @@ 
			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      power-domain = <&l2ccc_1>;

			      /* A53 L2 dump not supported */

			      qcom,dump-size = <0x0>;

			};

			L1_I_100: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};

			L1_D_100: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};

		};
@@ -75,6 +85,14 @@ 
			qcom,acc = <&acc1>;

			qcom,limits-info = <&mitigation_profile1>;

			next-level-cache = <&L2_1>;

			L1_I_101: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};

			L1_D_101: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};

		};



		CPU2: cpu@102 {
@@ -85,6 +103,14 @@ 
			qcom,acc = <&acc2>;

			qcom,limits-info = <&mitigation_profile2>;

			next-level-cache = <&L2_1>;

			L1_I_102: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};

			L1_D_102: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};

		};



		CPU3: cpu@103 {
@@ -95,6 +121,14 @@ 
			qcom,acc = <&acc3>;

			qcom,limits-info = <&mitigation_profile3>;

			next-level-cache = <&L2_1>;

			L1_I_103: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};

			L1_D_103: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};

		};



		CPU4: cpu@0 {
@@ -109,6 +143,15 @@ 
			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      power-domain = <&l2ccc_0>;

			      qcom,dump-size = <0x0>;

			};

			L1_I_0: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};

			L1_D_0: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};

		};
@@ -120,6 +163,14 @@ 
			qcom,acc = <&acc5>;

			qcom,limits-info = <&mitigation_profile4>;

			next-level-cache = <&L2_0>;

			L1_I_1: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};

			L1_D_1: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};

		};



		CPU6: cpu@2 {
@@ -130,6 +181,14 @@ 
			qcom,acc = <&acc6>;

			qcom,limits-info = <&mitigation_profile4>;

			next-level-cache = <&L2_0>;

			L1_I_2: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};

			L1_D_2: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};

		};



		CPU7: cpu@3 {
@@ -140,6 +199,14 @@ 
			qcom,acc = <&acc7>;

			qcom,limits-info = <&mitigation_profile4>;

			next-level-cache = <&L2_0>;

			L1_I_3: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};

			L1_D_3: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};

		};

	};

};
@@ -194,4 +261,83 @@ 
		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b1b8000 0x1000>;

	};



	cpuss_dump {

		compatible = "qcom,cpuss-dump";

		status = "disabled";

		qcom,l2_dump0 {

			/* L2 cache dump for A53 cluster */

			qcom,dump-node = <&L2_0>;

			qcom,dump-id = <0xC0>;

		};

		qcom,l2_dump1 {

			/* L2 cache dump for A53 cluster */

			qcom,dump-node = <&L2_1>;

			qcom,dump-id = <0xC1>;

		};

		qcom,l1_i_cache0 {

			qcom,dump-node = <&L1_I_0>;

			qcom,dump-id = <0x60>;

		};

		qcom,l1_i_cache1 {

			qcom,dump-node = <&L1_I_1>;

			qcom,dump-id = <0x61>;

		};

		qcom,l1_i_cache2 {

			qcom,dump-node = <&L1_I_2>;

			qcom,dump-id = <0x62>;

		};

		qcom,l1_i_cache3 {

			qcom,dump-node = <&L1_I_3>;

			qcom,dump-id = <0x63>;

		};

		qcom,l1_i_cache100 {

			qcom,dump-node = <&L1_I_100>;

			qcom,dump-id = <0x64>;

		};

		qcom,l1_i_cache101 {

			qcom,dump-node = <&L1_I_101>;

			qcom,dump-id = <0x65>;

		};

		qcom,l1_i_cache102 {

			qcom,dump-node = <&L1_I_102>;

			qcom,dump-id = <0x66>;

		};

		qcom,l1_i_cache103 {

			qcom,dump-node = <&L1_I_103>;

			qcom,dump-id = <0x67>;

		};

		qcom,l1_d_cache0 {

			qcom,dump-node = <&L1_D_0>;

			qcom,dump-id = <0x80>;

		};

		qcom,l1_d_cache1 {

			qcom,dump-node = <&L1_D_1>;

			qcom,dump-id = <0x81>;

		};

		qcom,l1_d_cache2 {

			qcom,dump-node = <&L1_D_2>;

			qcom,dump-id = <0x82>;

		};

		qcom,l1_d_cache3 {

			qcom,dump-node = <&L1_D_3>;

			qcom,dump-id = <0x83>;

		};

		qcom,l1_d_cache100 {

			qcom,dump-node = <&L1_D_100>;

			qcom,dump-id = <0x84>;

		};

		qcom,l1_d_cache101 {

			qcom,dump-node = <&L1_D_101>;

			qcom,dump-id = <0x85>;

		};

		qcom,l1_d_cache102 {

			qcom,dump-node = <&L1_D_102>;

			qcom,dump-id = <0x86>;

		};

		qcom,l1_d_cache103 {

			qcom,dump-node = <&L1_D_103>;

			qcom,dump-id = <0x87>;

		};

	};

};

arch/arm/boot/dts/qcom/msm8953-cpu.dtsi

+147 −0
Original line number Diff line number Diff line
@@ -65,6 +65,16 @@ 
			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      power-domain = <&l2ccc_0>;

			      /* A53 L2 dump not supported */

			      qcom,dump-size = <0x0>;

			};

			L1_I_0: l1-icache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x8800>;

			};

			L1_D_0: l1-dcache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x9000>;

			};

		};
@@ -77,6 +87,14 @@ 
			qcom,limits-info = <&mitigation_profile1>;

			qcom,ea = <&ea1>;

			next-level-cache = <&L2_0>;

			L1_I_1: l1-icache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x8800>;

			};

			L1_D_1: l1-dcache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x9000>;

			};

		};



		CPU2: cpu@2 {
@@ -88,6 +106,14 @@ 
			qcom,limits-info = <&mitigation_profile2>;

			qcom,ea = <&ea2>;

			next-level-cache = <&L2_0>;

			L1_I_2: l1-icache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x8800>;

			};

			L1_D_2: l1-dcache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x9000>;

			};

		};



		CPU3: cpu@3 {
@@ -99,6 +125,14 @@ 
			qcom,limits-info = <&mitigation_profile3>;

			qcom,ea = <&ea3>;

			next-level-cache = <&L2_0>;

			L1_I_3: l1-icache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x8800>;

			};

			L1_D_3: l1-dcache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x9000>;

			};

		};



		CPU4: cpu@100 {
@@ -114,6 +148,16 @@ 
			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      power-domain = <&l2ccc_1>;

			      /* A53 L2 dump not supported */

			      qcom,dump-size = <0x0>;

			};

			L1_I_100: l1-icache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x8800>;

			};

			L1_D_100: l1-dcache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x9000>;

			};

		};
@@ -126,6 +170,14 @@ 
			qcom,limits-info = <&mitigation_profile5>;

			qcom,ea = <&ea5>;

			next-level-cache = <&L2_1>;

			L1_I_101: l1-icache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x8800>;

			};

			L1_D_101: l1-dcache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x9000>;

			};

		};



		CPU6: cpu@102 {
@@ -137,6 +189,14 @@ 
			qcom,limits-info = <&mitigation_profile6>;

			qcom,ea = <&ea6>;

			next-level-cache = <&L2_1>;

			L1_I_102: l1-icache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x8800>;

			};

			L1_D_102: l1-dcache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x9000>;

			};

		};



		CPU7: cpu@103 {
@@ -148,6 +208,14 @@ 
			qcom,limits-info = <&mitigation_profile7>;

			qcom,ea = <&ea7>;

			next-level-cache = <&L2_1>;

			L1_I_103: l1-icache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x8800>;

			};

			L1_D_103: l1-dcache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x9000>;

			};

		};

	};

};
@@ -202,4 +270,83 @@ 
		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b0b8000 0x1000>;

	};



	cpuss_dump {

		compatible = "qcom,cpuss-dump";

		status = "disabled";

		qcom,l2_dump0 {

			/* L2 cache dump for A53 cluster */

			qcom,dump-node = <&L2_0>;

			qcom,dump-id = <0xC0>;

		};

		qcom,l2_dump1 {

			/* L2 cache dump for A53 cluster */

			qcom,dump-node = <&L2_1>;

			qcom,dump-id = <0xC1>;

		};

		qcom,l1_i_cache0 {

			qcom,dump-node = <&L1_I_0>;

			qcom,dump-id = <0x60>;

		};

		qcom,l1_i_cache1 {

			qcom,dump-node = <&L1_I_1>;

			qcom,dump-id = <0x61>;

		};

		qcom,l1_i_cache2 {

			qcom,dump-node = <&L1_I_2>;

			qcom,dump-id = <0x62>;

		};

		qcom,l1_i_cache3 {

			qcom,dump-node = <&L1_I_3>;

			qcom,dump-id = <0x63>;

		};

		qcom,l1_i_cache100 {

			qcom,dump-node = <&L1_I_100>;

			qcom,dump-id = <0x64>;

		};

		qcom,l1_i_cache101 {

			qcom,dump-node = <&L1_I_101>;

			qcom,dump-id = <0x65>;

		};

		qcom,l1_i_cache102 {

			qcom,dump-node = <&L1_I_102>;

			qcom,dump-id = <0x66>;

		};

		qcom,l1_i_cache103 {

			qcom,dump-node = <&L1_I_103>;

			qcom,dump-id = <0x67>;

		};

		qcom,l1_d_cache0 {

			qcom,dump-node = <&L1_D_0>;

			qcom,dump-id = <0x80>;

		};

		qcom,l1_d_cache1 {

			qcom,dump-node = <&L1_D_1>;

			qcom,dump-id = <0x81>;

		};

		qcom,l1_d_cache2 {

			qcom,dump-node = <&L1_D_2>;

			qcom,dump-id = <0x82>;

		};

		qcom,l1_d_cache3 {

			qcom,dump-node = <&L1_D_3>;

			qcom,dump-id = <0x83>;

		};

		qcom,l1_d_cache100 {

			qcom,dump-node = <&L1_D_100>;

			qcom,dump-id = <0x84>;

		};

		qcom,l1_d_cache101 {

			qcom,dump-node = <&L1_D_101>;

			qcom,dump-id = <0x85>;

		};

		qcom,l1_d_cache102 {

			qcom,dump-node = <&L1_D_102>;

			qcom,dump-id = <0x86>;

		};

		qcom,l1_d_cache103 {

			qcom,dump-node = <&L1_D_103>;

			qcom,dump-id = <0x87>;

		};

	};

};