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Commit c6938034 authored by Amit Atreya's avatar Amit Atreya Committed by Prasad Sodagudi
Browse files

ARM: dts: msm: Add support for MSMGOLD 



Add initial set of device tree and board files
to build the msmgold target.

Change-Id: I4bc2c6589e62443f32b8c353d5c082789dd6b378
Signed-off-by: default avatarAmit Atreya <aatrey@codeaurora.org>
Signed-off-by: default avatarPrasad Sodagudi <psodagud@codeaurora.org>
parent ec7db6c5

Documentation/devicetree/bindings/arm/msm/msm.txt

+4 −0
Original line number Diff line number Diff line
@@ -59,6 +59,9 @@ SoCs: 
- MSM8916

  compatible = "qcom,msm8916"



- MSMGOLD

  compatible = "qcom,msmgold"



- MSM8936

  compatible = "qcom,msm8936"
@@ -188,6 +191,7 @@ compatible = "qcom,msm8916-qrd-skuid" 
compatible = "qcom,msm8916-qrd-skut1"

compatible = "qcom,msm8916-rumi"

compatible = "qcom,msm8916-sim"

compatible = "qcom,msmgold-rumi"

compatible = "qcom,msm8926-cdp"

compatible = "qcom,msm8926-mtp"

compatible = "qcom,msm8926-qrd"

arch/arm/boot/dts/qcom/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -104,6 +104,8 @@ dtb-$(CONFIG_ARCH_MSM8937) += msm8937-rumi.dtb \ 
	apq8037-pmi8950-mtp.dtb \

	apq8037-pmi8937-mtp.dtb



dtb-$(CONFIG_ARCH_MSMGOLD) += msmgold-rumi.dtb



dtb-$(CONFIG_ARCH_MSMTITANIUM) += msmtitanium-sim.dtb \

	msmtitanium-rumi.dtb \

	msmtitanium-cdp.dtb \

arch/arm/boot/dts/qcom/msmgold-cpu.dtsi

0 → 100644
+109 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



/ {

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		cpu-map {



			cluster0 {

				core0 {

					cpu = <&CPU0>;

				};

				core1 {

					cpu = <&CPU1>;

				};

				core2 {

					cpu = <&CPU2>;

				};

				core3 {

					cpu = <&CPU3>;

				};

			};

		};



		CPU0: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x100>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			qcom,acc = <&acc0>;

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      power-domain = <&l2ccc_0>;

			};

		};



		CPU1: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x101>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			qcom,acc = <&acc1>;

			next-level-cache = <&L2_1>;

		};



		CPU2: cpu@102 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x102>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			qcom,acc = <&acc2>;

			next-level-cache = <&L2_1>;

		};



		CPU3: cpu@103 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x103>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			qcom,acc = <&acc3>;

			next-level-cache = <&L2_1>;

		};



	};

};



&soc {

	l2ccc_0: clock-controller@b011000 {

		compatible = "qcom,8937-l2ccc";

		reg = <0x0b011000 0x1000>;

	};



	acc0:clock-controller@b088000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b088000 0x1000>;

	};



	acc1:clock-controller@b098000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b098000 0x1000>;

	};



	acc2:clock-controller@b0a8000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b0a8000 0x1000>;

	};



	acc3:clock-controller@b0b8000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b0b8000 0x1000>;

	};

};

arch/arm/boot/dts/qcom/msmgold-pinctrl.dtsi

0 → 100644
+53 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&soc {

	tlmm: pinctrl@1000000 {

		compatible = "qcom,msmgold-pinctrl";

		reg = <0x1000000 0x300000>;

		interrupts = <0 208 0>;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;



		pmx-uartconsole {

			uart_console_active: uart_console_active {

				mux {

					pins = "gpio4", "gpio5";

					function = "blsp_uart2";

				};



				config {

					pins = "gpio4", "gpio5";

					drive-strength = <2>;

					bias-disable;

				};

			};



			uart_console_sleep: uart_console_sleep {

				mux {

					pins = "gpio4", "gpio5";

					function = "blsp_uart2";

				};



				config {

					pins = "gpio4", "gpio5";

					drive-strength = <2>;

					bias-pull-down;

				};

			};



		};

	};

};

arch/arm/boot/dts/qcom/msmgold-rumi.dts

0 → 100644
+40 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



/dts-v1/;



/memreserve/ 0x90000000 0x00000200;



#include "msmgold.dtsi"



/ {

	model = "Qualcomm Technologies, Inc. MSMGOLD RUMI";

	compatible = "qcom,msmgold-rumi", "qcom,msmgold", "qcom,rumi";

	qcom,board-id= <15 0>;

};



&soc {

	timer {

		clock-frequency = <10000000>;

	};

};



&blsp1_uart2 {

	status = "ok";

	pinctrl-names = "default";

	pinctrl-0 = <&uart_console_active>;

};



&clock_gcc {

	compatible = "qcom,dummycc";

};