Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c631715e authored by Deepak Katragadda's avatar Deepak Katragadda Committed by David Collins
Browse files

clk: msm: clock-cpu-8996: Add CPU clocks support for msm8996 Lite 



The CPU clock frequencies need to be updated for msm8996 Lite.
Add support for the new frequencies which are read based on
the bin fuse values.

Change-Id: Ief9aafac2a71ca45827f33a288d30428e8cd57cc
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 97e3761a

arch/arm/boot/dts/qcom/msm8996-v3.dtsi

+55 −0
Original line number Diff line number Diff line
@@ -395,6 +395,21 @@ 
			< 1401600000 14 >,

			< 1478400000 15 >,

			< 1593600000 16 >;

		qcom,pwrcl-speedbin1-v0 =

			<          0  0 >,

			<  307200000  1 >,

			<  422400000  2 >,

			<  480000000  3 >,

			<  556800000  4 >,

			<  652800000  5 >,

			<  729600000  6 >,

			<  844800000  7 >,

			<  960000000  8 >,

			< 1036800000  9 >,

			< 1113600000 10 >,

			< 1190400000 11 >,

			< 1228800000 12 >,

			< 1363200000 13 >;

		qcom,perfcl-speedbin0-v0 =

			<          0  0 >,

			<  307200000  1 >,
@@ -422,6 +437,29 @@ 
			< 1996800000 23 >,

			< 2073600000 24 >,

			< 2150400000 25 >;

		qcom,perfcl-speedbin1-v0 =

			<          0  0 >,

			<  307200000  1 >,

			<  403200000  2 >,

			<  480000000  3 >,

			<  556800000  4 >,

			<  652800000  5 >,

			<  729600000  6 >,

			<  806400000  7 >,

			<  883200000  8 >,

			<  940800000  9 >,

			< 1036800000 10 >,

			< 1113600000 11 >,

			< 1190400000 12 >,

			< 1248000000 13 >,

			< 1324800000 14 >,

			< 1401600000 15 >,

			< 1478400000 16 >,

			< 1555200000 17 >,

			< 1632000000 18 >,

			< 1708800000 19 >,

			< 1785600000 20 >,

			< 1804800000 21 >;

		qcom,cbf-speedbin0-v0 =

			<	   0  0 >,

			<  307200000  1 >,
@@ -443,6 +481,23 @@ 
			< 1459200000 17 >,

			< 1536000000 18 >,

			< 1593600000 19 >;

		qcom,cbf-speedbin1-v0 =

			<	   0  0 >,

			<  307200000  1 >,

			<  384000000  2 >,

			<  460800000  3 >,

			<  537600000  4 >,

			<  595200000  5 >,

			<  672000000  6 >,

			<  748800000  7 >,

			<  825600000  8 >,

			<  902400000  9 >,

			<  979200000 10 >,

			< 1056000000 11 >,

			< 1132800000 12 >,

			< 1190400000 13 >,

			< 1228800000 14 >,

			< 1305600000 15 >;

};



&msm_cpufreq {

arch/arm/boot/dts/qcom/msm8996.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -657,7 +657,7 @@ 
		      <0x06400000 0x1000>,

		      <0x06480000 0x1000>,

		      <0x09A11000 0x1000>,

		      <0x00070130    0x8>,

		      <0x00074130    0x8>,

		      <0x09820000 0x1000>;

		reg-names = "pwrcl_pll", "perfcl_pll", "cbf_pll", "pwrcl_mux", "perfcl_mux", "cbf_mux", "efuse", "debug";

		vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;

drivers/clk/msm/clock-cpu-8996.c

+34 −15
Original line number Diff line number Diff line
@@ -132,6 +132,9 @@ DEFINE_FIXED_SLAVE_DIV_CLK(sys_apcsaux_clk, 2, &sys_apcsaux_clk_gcc.c); 
#define L2ACDDVMRC_REG 0x584ULL

#define L2ACDSSCR_REG 0x589ULL



#define EFUSE_SHIFT	29

#define EFUSE_MASK	0x7



/* ACD static settings */

static int acdtd_val_pwrcl = 0x00006A11;

static int acdtd_val_perfcl = 0x00006A11;
@@ -1294,6 +1297,8 @@ static int cpu_clock_8996_driver_probe(struct platform_device *pdev) 
	int pvs_ver = 0;

	u32 pte_efuse;

	char perfclspeedbinstr[] = "qcom,perfcl-speedbinXX-vXX";

	char pwrclspeedbinstr[] = "qcom,pwrcl-speedbinXX-vXX";

	char cbfspeedbinstr[] = "qcom,cbf-speedbinXX-vXX";



	pwrcl_pll_main.c.flags = CLKFLAG_NO_RATE_CACHE;

	perfcl_pll_main.c.flags = CLKFLAG_NO_RATE_CACHE;
@@ -1307,16 +1312,9 @@ static int cpu_clock_8996_driver_probe(struct platform_device *pdev) 
		return ret;

	}



	ret = of_get_fmax_vdd_class(pdev, &pwrcl_clk.c,

				    "qcom,pwrcl-speedbin0-v0");

	if (ret) {

		dev_err(&pdev->dev, "Can't get speed bin for pwrcl\n");

		return ret;

	}



	pte_efuse = readl_relaxed(vbases[EFUSE_BASE]);

	perfclspeedbin = pte_efuse & 0x7;

	dev_info(&pdev->dev, "using perf speed bin %u and pvs_ver %d\n",

	perfclspeedbin = ((pte_efuse >> EFUSE_SHIFT) & EFUSE_MASK);

	dev_info(&pdev->dev, "using perf/pwr/cbf speed bin %u and pvs_ver %d\n",

		 perfclspeedbin, pvs_ver);



	snprintf(perfclspeedbinstr, ARRAY_SIZE(perfclspeedbinstr),
@@ -1333,12 +1331,33 @@ static int cpu_clock_8996_driver_probe(struct platform_device *pdev) 
		}

	}



	snprintf(pwrclspeedbinstr, ARRAY_SIZE(pwrclspeedbinstr),

			"qcom,pwrcl-speedbin%d-v%d", perfclspeedbin, pvs_ver);



	ret = of_get_fmax_vdd_class(pdev, &pwrcl_clk.c, pwrclspeedbinstr);

	if (ret) {

		dev_err(&pdev->dev, "Can't get speed bin for pwrcl. Falling back to zero.\n");

		ret = of_get_fmax_vdd_class(pdev, &pwrcl_clk.c,

				    "qcom,pwrcl-speedbin0-v0");

		if (ret) {

			dev_err(&pdev->dev, "Unable to retrieve plan for pwrcl\n");

			return ret;

		}

	}



	snprintf(cbfspeedbinstr, ARRAY_SIZE(cbfspeedbinstr),

			"qcom,cbf-speedbin%d-v%d", perfclspeedbin, pvs_ver);



	ret = of_get_fmax_vdd_class(pdev, &cbf_clk.c, cbfspeedbinstr);

	if (ret) {

		dev_err(&pdev->dev, "Can't get speed bin for cbf. Falling back to zero.\n");

		ret = of_get_fmax_vdd_class(pdev, &cbf_clk.c,

				    "qcom,cbf-speedbin0-v0");

		if (ret) {

		dev_err(&pdev->dev, "Can't get speed bin for cbf\n");

			dev_err(&pdev->dev, "Unable to retrieve plan for cbf\n");

			return ret;

		}

	}



	get_online_cpus();
@@ -1632,10 +1651,10 @@ int __init cpu_clock_8996_early_init(void) 
	__init_alpha_pll(&pwrcl_alt_pll.c);



	/* Set an appropriate rate on the perf clusters PLLs */

	perfcl_pll.c.ops->set_rate(&perfcl_pll.c, pwrcl_early_boot_rate);

	perfcl_pll.c.ops->set_rate(&perfcl_pll.c, perfcl_early_boot_rate);

	perfcl_alt_pll.c.ops->set_rate(&perfcl_alt_pll.c,

				       alt_pll_early_boot_rate);

	pwrcl_pll.c.ops->set_rate(&pwrcl_pll.c, perfcl_early_boot_rate);

	pwrcl_pll.c.ops->set_rate(&pwrcl_pll.c, pwrcl_early_boot_rate);

	pwrcl_alt_pll.c.ops->set_rate(&pwrcl_alt_pll.c,

				      alt_pll_early_boot_rate);