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Commit c61b5f3a authored by Devesh Jhunjhunwala's avatar Devesh Jhunjhunwala Committed by Santosh Mardi
Browse files

clk: msm: gcc-californium: Add support for apss_ahb_clk_src 



The apss_ahb_clk_src needs to be scaled along with the cpu
clock. Add support for this clock in the clock driver so
clients can use it to enable this.

CRs-Fixed: 980306
Change-Id: Ibbb420748e86e8d783c8da1680c5b8677d2729e5
Signed-off-by: default avatarDevesh Jhunjhunwala <deveshj@codeaurora.org>
parent e4aa3259

drivers/clk/msm/clock-gcc-californium.c

+29 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015, The Linux Foundation. All rights reserved.

 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -68,7 +68,9 @@ static void __iomem *virt_apcsbase; 
#define GCC_REG_BASE(x) (void __iomem *)(virt_base + (x))



#define xo_source_val 0

#define xo_a_clk_source_val 0

#define gpll0_out_main_cgc_source_val 1

#define gpll0_ao_out_main_cgc_source_val 1

#define gpll0_out_main_div2_cgc_source_val 2



#define FIXDIV(div) (div ? (2 * (div) - 1) : (0))
@@ -141,6 +143,7 @@ static DEFINE_VDD_REGULATORS(vdd_dig_ao, VDD_DIG_NUM, 1, vdd_corner, NULL); 
#define APCS_GPLL_ENA_VOTE                               (0x45000)

#define APCS_CLOCK_BRANCH_ENA_VOTE                       (0x45004)

#define APCS_SMMU_CLOCK_BRANCH_ENA_VOTE                  (0x4500C)

#define APSS_AHB_CMD_RCGR                                (0x46000)

#define GCC_DEBUG_CLK_CTL                                (0x74000)

#define CLOCK_FRQ_MEASURE_CTL                            (0x74004)

#define CLOCK_FRQ_MEASURE_STATUS                         (0x74008)
@@ -294,6 +297,7 @@ static struct pll_vote_clk gpll0_ao = { 
};



DEFINE_EXT_CLK(gpll0_out_main_cgc, &gpll0.c);

DEFINE_EXT_CLK(gpll0_ao_out_main_cgc, &gpll0_ao.c);



DEFINE_FIXED_DIV_CLK(gpll0_out_main_div2_cgc, 2, &gpll0.c);
@@ -309,6 +313,29 @@ static struct gate_clk gpll0_out_msscc = { 
	},

};



static struct clk_freq_tbl ftbl_apss_ahb_clk_src[] = {

	F(  19200000,         xo_a_clk,    1,    0,     0),

	F(  50000000, gpll0_ao_out_main_cgc,   12,    0,     0),

	F( 100000000, gpll0_ao_out_main_cgc,    6,    0,     0),

	F( 133333333, gpll0_ao_out_main_cgc,  4.5,    0,     0),

	F_END

};



static struct rcg_clk apss_ahb_clk_src = {

	.cmd_rcgr_reg = APSS_AHB_CMD_RCGR,

	.set_rate = set_rate_hid,

	.freq_tbl = ftbl_apss_ahb_clk_src,

	.current_freq = &rcg_dummy_freq,

	.base = &virt_base,

	.c = {

		.dbg_name = "apss_ahb_clk_src",

		.ops = &clk_ops_rcg,

		VDD_DIG_FMAX_MAP4(LOWER, 19200000, LOW, 50000000,

				  NOMINAL, 100000000, HIGH, 133333333),

		CLK_INIT(apss_ahb_clk_src.c),

	},

};



static struct clk_freq_tbl ftbl_usb30_master_clk_src[] = {

	F(  60000000, gpll0_out_main_div2_cgc,    5,    0,     0),

	F( 120000000, gpll0_out_main_cgc,    5,    0,     0),
@@ -1433,6 +1460,7 @@ static struct clk_lookup msm_clocks_gcc_californium[] = { 
	CLK_LIST(gpll0_out_main_cgc),

	CLK_LIST(gpll0_out_main_div2_cgc),

	CLK_LIST(gpll0_out_msscc),

	CLK_LIST(apss_ahb_clk_src),

	CLK_LIST(usb30_master_clk_src),

	CLK_LIST(blsp1_qup1_i2c_apps_clk_src),

	CLK_LIST(blsp1_qup1_spi_apps_clk_src),

include/dt-bindings/clock/msm-clocks-californium.h

+2 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015, The Linux Foundation. All rights reserved.

 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -69,6 +69,7 @@ 
#define clk_gpll0 0x1ebe3bc4

#define clk_gpll0_ao 0xa1368304

#define clk_gpll0_out_msscc 0x7d794829

#define clk_apss_ahb_clk_src 0x36f8495f

#define clk_usb30_master_clk_src 0xc6262f89

#define clk_blsp1_qup1_i2c_apps_clk_src 0x17f78f5e

#define clk_blsp1_qup1_spi_apps_clk_src 0xf534c4fa