Loading drivers/usb/dwc3/dwc3-msm.c +14 −2 Original line number Diff line number Diff line Loading @@ -97,6 +97,8 @@ MODULE_PARM_DESC(dcp_max_current, "max current drawn for DCP charger"); #define CGCTL_REG (QSCRATCH_REG_OFFSET + 0x28) #define PWR_EVNT_IRQ_STAT_REG (QSCRATCH_REG_OFFSET + 0x58) #define PWR_EVNT_IRQ_MASK_REG (QSCRATCH_REG_OFFSET + 0x5C) #define QSCRATCH_USB30_STS_REG (QSCRATCH_REG_OFFSET + 0xF8) #define PWR_EVNT_POWERDOWN_IN_P3_MASK BIT(2) #define PWR_EVNT_POWERDOWN_OUT_P3_MASK BIT(3) Loading Loading @@ -1879,6 +1881,7 @@ static int dwc3_msm_prepare_suspend(struct dwc3_msm *mdwc) { unsigned long timeout; u32 reg = 0; struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); if ((mdwc->in_host_mode || (mdwc->vbus_active && mdwc->otg_state == OTG_STATE_B_SUSPEND)) Loading Loading @@ -1908,9 +1911,18 @@ static int dwc3_msm_prepare_suspend(struct dwc3_msm *mdwc) if (!(reg & PWR_EVNT_LPM_IN_L2_MASK)) { dev_err(mdwc->dev, "could not transition HS PHY to L2\n"); queue_delayed_work(mdwc->dwc3_wq, &mdwc->resume_work, 0); dbg_event(0xFF, "PWR_EVNT_LPM", dwc3_msm_read_reg(mdwc->base, PWR_EVNT_IRQ_STAT_REG)); dbg_event(0xFF, "QUSB_STS", dwc3_msm_read_reg(mdwc->base, QSCRATCH_USB30_STS_REG)); /* Mark fatal error for host mode or USB bus suspend case */ if (mdwc->in_host_mode || (mdwc->vbus_active && mdwc->otg_state == OTG_STATE_B_SUSPEND)) { queue_delayed_work(mdwc->dwc3_wq, &mdwc->resume_work, 0); return -EBUSY; } } /* Clear L2 event bit */ dwc3_msm_write_reg(mdwc->base, PWR_EVNT_IRQ_STAT_REG, Loading Loading
drivers/usb/dwc3/dwc3-msm.c +14 −2 Original line number Diff line number Diff line Loading @@ -97,6 +97,8 @@ MODULE_PARM_DESC(dcp_max_current, "max current drawn for DCP charger"); #define CGCTL_REG (QSCRATCH_REG_OFFSET + 0x28) #define PWR_EVNT_IRQ_STAT_REG (QSCRATCH_REG_OFFSET + 0x58) #define PWR_EVNT_IRQ_MASK_REG (QSCRATCH_REG_OFFSET + 0x5C) #define QSCRATCH_USB30_STS_REG (QSCRATCH_REG_OFFSET + 0xF8) #define PWR_EVNT_POWERDOWN_IN_P3_MASK BIT(2) #define PWR_EVNT_POWERDOWN_OUT_P3_MASK BIT(3) Loading Loading @@ -1879,6 +1881,7 @@ static int dwc3_msm_prepare_suspend(struct dwc3_msm *mdwc) { unsigned long timeout; u32 reg = 0; struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); if ((mdwc->in_host_mode || (mdwc->vbus_active && mdwc->otg_state == OTG_STATE_B_SUSPEND)) Loading Loading @@ -1908,9 +1911,18 @@ static int dwc3_msm_prepare_suspend(struct dwc3_msm *mdwc) if (!(reg & PWR_EVNT_LPM_IN_L2_MASK)) { dev_err(mdwc->dev, "could not transition HS PHY to L2\n"); queue_delayed_work(mdwc->dwc3_wq, &mdwc->resume_work, 0); dbg_event(0xFF, "PWR_EVNT_LPM", dwc3_msm_read_reg(mdwc->base, PWR_EVNT_IRQ_STAT_REG)); dbg_event(0xFF, "QUSB_STS", dwc3_msm_read_reg(mdwc->base, QSCRATCH_USB30_STS_REG)); /* Mark fatal error for host mode or USB bus suspend case */ if (mdwc->in_host_mode || (mdwc->vbus_active && mdwc->otg_state == OTG_STATE_B_SUSPEND)) { queue_delayed_work(mdwc->dwc3_wq, &mdwc->resume_work, 0); return -EBUSY; } } /* Clear L2 event bit */ dwc3_msm_write_reg(mdwc->base, PWR_EVNT_IRQ_STAT_REG, Loading