Loading arch/arm/mach-zynq/common.c +1 −1 Original line number Diff line number Diff line Loading @@ -78,7 +78,7 @@ static void __init xilinx_zynq_timer_init(void) xilinx_zynq_clocks_init(slcr); xttcps_timer_init(); clocksource_of_init(); } /** Loading arch/arm/mach-zynq/common.h +0 −2 Original line number Diff line number Diff line Loading @@ -17,6 +17,4 @@ #ifndef __MACH_ZYNQ_COMMON_H__ #define __MACH_ZYNQ_COMMON_H__ void __init xttcps_timer_init(void); #endif arch/arm/mach-zynq/timer.c +20 −23 Original line number Diff line number Diff line Loading @@ -22,7 +22,6 @@ #include <linux/of_irq.h> #include <linux/slab.h> #include <linux/clk-provider.h> #include "common.h" /* * This driver configures the 2 16-bit count-up timers as follows: Loading Loading @@ -260,8 +259,10 @@ static void __init xttc_setup_clocksource(struct clk *clk, void __iomem *base) ttccs->xttc.clk = clk; err = clk_prepare_enable(ttccs->xttc.clk); if (WARN_ON(err)) if (WARN_ON(err)) { kfree(ttccs); return; } ttccs->xttc.clk_rate_change_nb.notifier_call = xttcps_rate_change_clocksource_cb; Loading Loading @@ -290,9 +291,10 @@ static void __init xttc_setup_clocksource(struct clk *clk, void __iomem *base) err = clocksource_register_hz(&ttccs->cs, clk_get_rate(ttccs->xttc.clk) / PRESCALE); if (WARN_ON(err)) if (WARN_ON(err)) { kfree(ttccs); return; } } static int xttcps_rate_change_clockevent_cb(struct notifier_block *nb, Loading Loading @@ -341,8 +343,10 @@ static void __init xttc_setup_clockevent(struct clk *clk, ttcce->xttc.clk = clk; err = clk_prepare_enable(ttcce->xttc.clk); if (WARN_ON(err)) if (WARN_ON(err)) { kfree(ttcce); return; } ttcce->xttc.clk_rate_change_nb.notifier_call = xttcps_rate_change_clockevent_cb; Loading Loading @@ -373,8 +377,10 @@ static void __init xttc_setup_clockevent(struct clk *clk, err = request_irq(irq, xttcps_clock_event_interrupt, IRQF_DISABLED | IRQF_TIMER, ttcce->ce.name, ttcce); if (WARN_ON(err)) if (WARN_ON(err)) { kfree(ttcce); return; } clockevents_config_and_register(&ttcce->ce, clk_get_rate(ttcce->xttc.clk) / PRESCALE, 1, 0xfffe); Loading @@ -386,11 +392,17 @@ static void __init xttc_setup_clockevent(struct clk *clk, * Initializes the timer hardware and register the clock source and clock event * timers with Linux kernal timer framework */ static void __init xttcps_timer_init_of(struct device_node *timer) static void __init xttcps_timer_init(struct device_node *timer) { unsigned int irq; void __iomem *timer_baseaddr; struct clk *clk; static int initialized; if (initialized) return; initialized = 1; /* * Get the 1st Triple Timer Counter (TTC) block from the device tree Loading Loading @@ -421,19 +433,4 @@ static void __init xttcps_timer_init_of(struct device_node *timer) pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq); } void __init xttcps_timer_init(void) { const char * const timer_list[] = { "cdns,ttc", NULL }; struct device_node *timer; timer = of_find_compatible_node(NULL, NULL, timer_list[0]); if (!timer) { pr_err("ERROR: no compatible timer found\n"); BUG(); } xttcps_timer_init_of(timer); } CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", xttcps_timer_init); Loading
arch/arm/mach-zynq/common.c +1 −1 Original line number Diff line number Diff line Loading @@ -78,7 +78,7 @@ static void __init xilinx_zynq_timer_init(void) xilinx_zynq_clocks_init(slcr); xttcps_timer_init(); clocksource_of_init(); } /** Loading
arch/arm/mach-zynq/common.h +0 −2 Original line number Diff line number Diff line Loading @@ -17,6 +17,4 @@ #ifndef __MACH_ZYNQ_COMMON_H__ #define __MACH_ZYNQ_COMMON_H__ void __init xttcps_timer_init(void); #endif
arch/arm/mach-zynq/timer.c +20 −23 Original line number Diff line number Diff line Loading @@ -22,7 +22,6 @@ #include <linux/of_irq.h> #include <linux/slab.h> #include <linux/clk-provider.h> #include "common.h" /* * This driver configures the 2 16-bit count-up timers as follows: Loading Loading @@ -260,8 +259,10 @@ static void __init xttc_setup_clocksource(struct clk *clk, void __iomem *base) ttccs->xttc.clk = clk; err = clk_prepare_enable(ttccs->xttc.clk); if (WARN_ON(err)) if (WARN_ON(err)) { kfree(ttccs); return; } ttccs->xttc.clk_rate_change_nb.notifier_call = xttcps_rate_change_clocksource_cb; Loading Loading @@ -290,9 +291,10 @@ static void __init xttc_setup_clocksource(struct clk *clk, void __iomem *base) err = clocksource_register_hz(&ttccs->cs, clk_get_rate(ttccs->xttc.clk) / PRESCALE); if (WARN_ON(err)) if (WARN_ON(err)) { kfree(ttccs); return; } } static int xttcps_rate_change_clockevent_cb(struct notifier_block *nb, Loading Loading @@ -341,8 +343,10 @@ static void __init xttc_setup_clockevent(struct clk *clk, ttcce->xttc.clk = clk; err = clk_prepare_enable(ttcce->xttc.clk); if (WARN_ON(err)) if (WARN_ON(err)) { kfree(ttcce); return; } ttcce->xttc.clk_rate_change_nb.notifier_call = xttcps_rate_change_clockevent_cb; Loading Loading @@ -373,8 +377,10 @@ static void __init xttc_setup_clockevent(struct clk *clk, err = request_irq(irq, xttcps_clock_event_interrupt, IRQF_DISABLED | IRQF_TIMER, ttcce->ce.name, ttcce); if (WARN_ON(err)) if (WARN_ON(err)) { kfree(ttcce); return; } clockevents_config_and_register(&ttcce->ce, clk_get_rate(ttcce->xttc.clk) / PRESCALE, 1, 0xfffe); Loading @@ -386,11 +392,17 @@ static void __init xttc_setup_clockevent(struct clk *clk, * Initializes the timer hardware and register the clock source and clock event * timers with Linux kernal timer framework */ static void __init xttcps_timer_init_of(struct device_node *timer) static void __init xttcps_timer_init(struct device_node *timer) { unsigned int irq; void __iomem *timer_baseaddr; struct clk *clk; static int initialized; if (initialized) return; initialized = 1; /* * Get the 1st Triple Timer Counter (TTC) block from the device tree Loading Loading @@ -421,19 +433,4 @@ static void __init xttcps_timer_init_of(struct device_node *timer) pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq); } void __init xttcps_timer_init(void) { const char * const timer_list[] = { "cdns,ttc", NULL }; struct device_node *timer; timer = of_find_compatible_node(NULL, NULL, timer_list[0]); if (!timer) { pr_err("ERROR: no compatible timer found\n"); BUG(); } xttcps_timer_init_of(timer); } CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", xttcps_timer_init);