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Commit c42a2634 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'sh-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.x 

* 'sh-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.x:
  sh: fix the compile error in setup-sh7757.c
  serial: sh-sci: report CTS as active for get_mctrl
  sh: Add unaligned memory access for PC relative intructions
  sh: Fix unaligned memory access for branches without delay slots
  sh: Fix up fallout from cpuidle changes.
  serial: sh-sci: console Runtime PM support
  sh: Fix conflicting definitions of ptrace_triggered
  serial: sh-sci: fix DMA build by including dma-mapping.h
  serial: sh-sci: Fix up default regtype probing.
  sh: intc: enable both edges GPIO interrupts on sh7372
  shwdt: fix usage of mod_timer
  clocksource: sh_cmt: wait for CMCNT on init V2
parents f9557a44 21d41f2b

arch/sh/include/asm/ptrace.h

+1 −1
Original line number Diff line number Diff line
@@ -123,7 +123,7 @@ static inline unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, 
struct perf_event;

struct perf_sample_data;



extern void ptrace_triggered(struct perf_event *bp, int nmi,

extern void ptrace_triggered(struct perf_event *bp,

		      struct perf_sample_data *data, struct pt_regs *regs);



#define task_pt_regs(task) \

arch/sh/kernel/cpu/sh4a/setup-sh7757.c

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <linux/serial_sci.h>

#include <linux/io.h>

#include <linux/mm.h>

#include <linux/dma-mapping.h>

#include <linux/sh_timer.h>

#include <linux/sh_dma.h>

arch/sh/kernel/idle.c

+1 −1
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ 
#include <linux/atomic.h>

#include <asm/smp.h>



static void (*pm_idle)(void);

void (*pm_idle)(void);



static int hlt_counter;

arch/sh/kernel/traps_32.c

+37 −0
Original line number Diff line number Diff line
@@ -316,6 +316,35 @@ static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs, 
			break;

		}

		break;



	case 9: /* mov.w @(disp,PC),Rn */

		srcu = (unsigned char __user *)regs->pc;

		srcu += 4;

		srcu += (instruction & 0x00FF) << 1;

		dst = (unsigned char *)rn;

		*(unsigned long *)dst = 0;



#if !defined(__LITTLE_ENDIAN__)

		dst += 2;

#endif



		if (ma->from(dst, srcu, 2))

			goto fetch_fault;

		sign_extend(2, dst);

		ret = 0;

		break;



	case 0xd: /* mov.l @(disp,PC),Rn */

		srcu = (unsigned char __user *)(regs->pc & ~0x3);

		srcu += 4;

		srcu += (instruction & 0x00FF) << 2;

		dst = (unsigned char *)rn;

		*(unsigned long *)dst = 0;



		if (ma->from(dst, srcu, 4))

			goto fetch_fault;

		ret = 0;

		break;

	}

	return ret;
@@ -466,6 +495,7 @@ int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, 
		case 0x0500: /* mov.w @(disp,Rm),R0 */

			goto simple;

		case 0x0B00: /* bf   lab - no delayslot*/

			ret = 0;

			break;

		case 0x0F00: /* bf/s lab */

			ret = handle_delayslot(regs, instruction, ma);
@@ -479,6 +509,7 @@ int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, 
			}

			break;

		case 0x0900: /* bt   lab - no delayslot */

			ret = 0;

			break;

		case 0x0D00: /* bt/s lab */

			ret = handle_delayslot(regs, instruction, ma);
@@ -494,6 +525,9 @@ int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, 
		}

		break;



	case 0x9000: /* mov.w @(disp,Rm),Rn */

		goto simple;



	case 0xA000: /* bra label */

		ret = handle_delayslot(regs, instruction, ma);

		if (ret==0)
@@ -507,6 +541,9 @@ int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, 
			regs->pc += SH_PC_12BIT_OFFSET(instruction);

		}

		break;



	case 0xD000: /* mov.l @(disp,Rm),Rn */

		goto simple;

	}

	return ret;

drivers/clocksource/sh_cmt.c

+32 −2
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
#include <linux/clk.h>

#include <linux/irq.h>

#include <linux/err.h>

#include <linux/delay.h>

#include <linux/clocksource.h>

#include <linux/clockchips.h>

#include <linux/sh_timer.h>
@@ -150,13 +151,13 @@ static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start) 


static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)

{

	int ret;

	int k, ret;



	/* enable clock */

	ret = clk_enable(p->clk);

	if (ret) {

		dev_err(&p->pdev->dev, "cannot enable clock\n");

		return ret;

		goto err0;

	}



	/* make sure channel is disabled */
@@ -174,9 +175,38 @@ static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate) 
	sh_cmt_write(p, CMCOR, 0xffffffff);

	sh_cmt_write(p, CMCNT, 0);



	/*

	 * According to the sh73a0 user's manual, as CMCNT can be operated

	 * only by the RCLK (Pseudo 32 KHz), there's one restriction on

	 * modifying CMCNT register; two RCLK cycles are necessary before

	 * this register is either read or any modification of the value

	 * it holds is reflected in the LSI's actual operation.

	 *

	 * While at it, we're supposed to clear out the CMCNT as of this

	 * moment, so make sure it's processed properly here.  This will

	 * take RCLKx2 at maximum.

	 */

	for (k = 0; k < 100; k++) {

		if (!sh_cmt_read(p, CMCNT))

			break;

		udelay(1);

	}



	if (sh_cmt_read(p, CMCNT)) {

		dev_err(&p->pdev->dev, "cannot clear CMCNT\n");

		ret = -ETIMEDOUT;

		goto err1;

	}



	/* enable channel */

	sh_cmt_start_stop_ch(p, 1);

	return 0;

 err1:

	/* stop clock */

	clk_disable(p->clk);



 err0:

	return ret;

}



static void sh_cmt_disable(struct sh_cmt_priv *p)