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Commit c3e59d1e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (31 commits)
  [MIPS] Remove duplicate ISA DMA code for 0 DMA channel case.
  [MIPS] Remove unused definition of cpu_to_lelongp()
  [MIPS] Remove userspace proofing from <asm/bitops.h>.
  [MIPS] Remove old junk left from old atomic_lock.
  [MIPS] Use conditional traps for BUG_ON on MIPS II and better.
  [MIPS] mips HPT cleanup: make clocksource_mips public
  [MIPS] do_IRQ cleanup
  [MIPS] Avoid dupliate D-cache flush on R400C / R4400 SC and MC variants.
  [MIPS] Remove redundant r4k_blast_icache() calls
  [MIPS] Work around bogus gcc warnings.
  [MIPS] Fix double inclusions
  [MIPS] use generic_handle_irq, handle_level_irq, handle_percpu_irq
  [MIPS] IRQ cleanups
  [MIPS] mips hpt cleanup: get rid of mips_hpt_init
  [MIPS] PB1200: Remove duplicate definitions
  [MIPS] Fix alignment hole in struct cache_desc; shrink struct.
  [MIPS] Oprofile: kernel support for the R10000.
  [MIPS] Remove unused R10000 performance counter definitions.
  [MIPS] Add support for kexec
  [MIPS] Don't print presence of WAIT instruction on bootup.
  ...
parents b07e3c3a aa414dff

arch/mips/Kconfig

+23 −5
Original line number Diff line number Diff line
@@ -266,8 +266,8 @@ config MIPS_MALTA 
	select BOOT_ELF32

	select HAVE_STD_PC_SERIAL_PORT

	select DMA_NONCOHERENT

	select IRQ_CPU

	select GENERIC_ISA_DMA

	select IRQ_CPU

	select HW_HAS_PCI

	select I8259

	select MIPS_BOARDS_GEN
@@ -534,7 +534,7 @@ config SGI_IP22 
	select HW_HAS_EISA

	select IP22_CPU_SCACHE

	select IRQ_CPU

	select NO_ISA if ISA

	select GENERIC_ISA_DMA_SUPPORT_BROKEN

	select SWAP_IO_SPACE

	select SYS_HAS_CPU_R4X00

	select SYS_HAS_CPU_R5000
@@ -766,6 +766,23 @@ config TOSHIBA_RBTX4938 


endchoice



config KEXEC

 	bool "Kexec system call (EXPERIMENTAL)"

 	depends on EXPERIMENTAL

 	help

 	  kexec is a system call that implements the ability to shutdown your

 	  current kernel, and to start another kernel.  It is like a reboot

 	  but it is indepedent of the system firmware.   And like a reboot

 	  you can start any kernel with it, not just Linux.



 	  The name comes from the similiarity to the exec system call.



 	  It is an ongoing process to be certain the hardware in a machine

 	  is properly shutdown, so do not be surprised if this code does not

 	  initially work for you.  It may help to enable device hotplugging

 	  support.  As of this writing the exact hardware interface is

 	  strongly in flux, so no good recommendation can be made.



source "arch/mips/ddb5xxx/Kconfig"

source "arch/mips/gt64120/ev64120/Kconfig"

source "arch/mips/jazz/Kconfig"
@@ -864,6 +881,9 @@ config MIPS_NILE4 
config MIPS_DISABLE_OBSOLETE_IDE

	bool



config GENERIC_ISA_DMA_SUPPORT_BROKEN

	bool



#

# Endianess selection.  Sufficiently obscure so many users don't know what to

# answer,so we try hard to limit the available choices.  Also the use of a
@@ -1835,13 +1855,11 @@ source "drivers/pci/Kconfig" 
config ISA

	bool



config NO_ISA

	bool



config EISA

	bool "EISA support"

	depends on HW_HAS_EISA

	select ISA

	select GENERIC_ISA_DMA

	---help---

	  The Extended Industry Standard Architecture (EISA) bus was

	  developed as an open alternative to the IBM MicroChannel bus.

arch/mips/Makefile

+1 −3
Original line number Diff line number Diff line
@@ -63,9 +63,7 @@ cflags-y += -mabi=64 
ifdef CONFIG_BUILD_ELF64

cflags-y		+= $(call cc-option,-mno-explicit-relocs)

else

# -msym32 can not be used for modules since they are loaded into XKSEG

CFLAGS_MODULE		+= $(call cc-option,-mno-explicit-relocs)

CFLAGS_KERNEL		+= $(call cc-option,-msym32)

cflags-y		+= $(call cc-option,-msym32)

endif

endif

arch/mips/au1000/common/irq.c

+22 −41
Original line number Diff line number Diff line
@@ -70,7 +70,6 @@ extern irq_cpustat_t irq_stat [NR_CPUS]; 
extern void mips_timer_interrupt(void);



static void setup_local_irq(unsigned int irq, int type, int int_req);

static unsigned int startup_irq(unsigned int irq);

static void end_irq(unsigned int irq_nr);

static inline void mask_and_ack_level_irq(unsigned int irq_nr);

static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr);
@@ -84,20 +83,6 @@ void (*board_init_irq)(void); 
static DEFINE_SPINLOCK(irq_lock);





static unsigned int startup_irq(unsigned int irq_nr)

{

	local_enable_irq(irq_nr);

	return 0;

}





static void shutdown_irq(unsigned int irq_nr)

{

	local_disable_irq(irq_nr);

	return;

}





inline void local_enable_irq(unsigned int irq_nr)

{

	if (irq_nr > AU1000_LAST_INTC0_INT) {
@@ -249,41 +234,37 @@ void restore_local_and_enable(int controller, unsigned long mask) 


static struct irq_chip rise_edge_irq_type = {

	.typename = "Au1000 Rise Edge",

	.startup = startup_irq,

	.shutdown = shutdown_irq,

	.enable = local_enable_irq,

	.disable = local_disable_irq,

	.ack = mask_and_ack_rise_edge_irq,

	.mask = local_disable_irq,

	.mask_ack = mask_and_ack_rise_edge_irq,

	.unmask = local_enable_irq,

	.end = end_irq,

};



static struct irq_chip fall_edge_irq_type = {

	.typename = "Au1000 Fall Edge",

	.startup = startup_irq,

	.shutdown = shutdown_irq,

	.enable = local_enable_irq,

	.disable = local_disable_irq,

	.ack = mask_and_ack_fall_edge_irq,

	.mask = local_disable_irq,

	.mask_ack = mask_and_ack_fall_edge_irq,

	.unmask = local_enable_irq,

	.end = end_irq,

};



static struct irq_chip either_edge_irq_type = {

	.typename = "Au1000 Rise or Fall Edge",

	.startup = startup_irq,

	.shutdown = shutdown_irq,

	.enable = local_enable_irq,

	.disable = local_disable_irq,

	.ack = mask_and_ack_either_edge_irq,

	.mask = local_disable_irq,

	.mask_ack = mask_and_ack_either_edge_irq,

	.unmask = local_enable_irq,

	.end = end_irq,

};



static struct irq_chip level_irq_type = {

	.typename = "Au1000 Level",

	.startup = startup_irq,

	.shutdown = shutdown_irq,

	.enable = local_enable_irq,

	.disable = local_disable_irq,

	.ack = mask_and_ack_level_irq,

	.mask = local_disable_irq,

	.mask_ack = mask_and_ack_level_irq,

	.unmask = local_enable_irq,

	.end = end_irq,

};
@@ -328,31 +309,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req) 
				au_writel(1<<(irq_nr-32), IC1_CFG2CLR);

				au_writel(1<<(irq_nr-32), IC1_CFG1CLR);

				au_writel(1<<(irq_nr-32), IC1_CFG0SET);

				irq_desc[irq_nr].chip = &rise_edge_irq_type;

				set_irq_chip(irq_nr, &rise_edge_irq_type);

				break;

			case INTC_INT_FALL_EDGE: /* 0:1:0 */

				au_writel(1<<(irq_nr-32), IC1_CFG2CLR);

				au_writel(1<<(irq_nr-32), IC1_CFG1SET);

				au_writel(1<<(irq_nr-32), IC1_CFG0CLR);

				irq_desc[irq_nr].chip = &fall_edge_irq_type;

				set_irq_chip(irq_nr, &fall_edge_irq_type);

				break;

			case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */

				au_writel(1<<(irq_nr-32), IC1_CFG2CLR);

				au_writel(1<<(irq_nr-32), IC1_CFG1SET);

				au_writel(1<<(irq_nr-32), IC1_CFG0SET);

				irq_desc[irq_nr].chip = &either_edge_irq_type;

				set_irq_chip(irq_nr, &either_edge_irq_type);

				break;

			case INTC_INT_HIGH_LEVEL: /* 1:0:1 */

				au_writel(1<<(irq_nr-32), IC1_CFG2SET);

				au_writel(1<<(irq_nr-32), IC1_CFG1CLR);

				au_writel(1<<(irq_nr-32), IC1_CFG0SET);

				irq_desc[irq_nr].chip = &level_irq_type;

				set_irq_chip(irq_nr, &level_irq_type);

				break;

			case INTC_INT_LOW_LEVEL: /* 1:1:0 */

				au_writel(1<<(irq_nr-32), IC1_CFG2SET);

				au_writel(1<<(irq_nr-32), IC1_CFG1SET);

				au_writel(1<<(irq_nr-32), IC1_CFG0CLR);

				irq_desc[irq_nr].chip = &level_irq_type;

				set_irq_chip(irq_nr, &level_irq_type);

				break;

			case INTC_INT_DISABLED: /* 0:0:0 */

				au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
@@ -380,31 +361,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req) 
				au_writel(1<<irq_nr, IC0_CFG2CLR);

				au_writel(1<<irq_nr, IC0_CFG1CLR);

				au_writel(1<<irq_nr, IC0_CFG0SET);

				irq_desc[irq_nr].chip = &rise_edge_irq_type;

				set_irq_chip(irq_nr, &rise_edge_irq_type);

				break;

			case INTC_INT_FALL_EDGE: /* 0:1:0 */

				au_writel(1<<irq_nr, IC0_CFG2CLR);

				au_writel(1<<irq_nr, IC0_CFG1SET);

				au_writel(1<<irq_nr, IC0_CFG0CLR);

				irq_desc[irq_nr].chip = &fall_edge_irq_type;

				set_irq_chip(irq_nr, &fall_edge_irq_type);

				break;

			case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */

				au_writel(1<<irq_nr, IC0_CFG2CLR);

				au_writel(1<<irq_nr, IC0_CFG1SET);

				au_writel(1<<irq_nr, IC0_CFG0SET);

				irq_desc[irq_nr].chip = &either_edge_irq_type;

				set_irq_chip(irq_nr, &either_edge_irq_type);

				break;

			case INTC_INT_HIGH_LEVEL: /* 1:0:1 */

				au_writel(1<<irq_nr, IC0_CFG2SET);

				au_writel(1<<irq_nr, IC0_CFG1CLR);

				au_writel(1<<irq_nr, IC0_CFG0SET);

				irq_desc[irq_nr].chip = &level_irq_type;

				set_irq_chip(irq_nr, &level_irq_type);

				break;

			case INTC_INT_LOW_LEVEL: /* 1:1:0 */

				au_writel(1<<irq_nr, IC0_CFG2SET);

				au_writel(1<<irq_nr, IC0_CFG1SET);

				au_writel(1<<irq_nr, IC0_CFG0CLR);

				irq_desc[irq_nr].chip = &level_irq_type;

				set_irq_chip(irq_nr, &level_irq_type);

				break;

			case INTC_INT_DISABLED: /* 0:0:0 */

				au_writel(1<<irq_nr, IC0_CFG0CLR);

arch/mips/au1000/pb1200/board_setup.c

+2 −6
Original line number Diff line number Diff line
@@ -151,12 +151,8 @@ void __init board_setup(void) 
#endif



	/* Setup Pb1200 External Interrupt Controller */

	{

		extern void (*board_init_irq)(void);

		extern void _board_init_irq(void);

	board_init_irq = _board_init_irq;

}

}



int

board_au1200fb_panel (void)

arch/mips/cobalt/irq.c

+14 −17
Original line number Diff line number Diff line
@@ -45,25 +45,22 @@ static inline void galileo_irq(void) 
{

	unsigned int mask, pending, devfn;



	mask = GALILEO_INL(GT_INTRMASK_OFS);

	pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask;

	mask = GT_READ(GT_INTRMASK_OFS);

	pending = GT_READ(GT_INTRCAUSE_OFS) & mask;



	if (pending & GALILEO_INTR_T0EXP) {



		GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS);

	if (pending & GT_INTR_T0EXP_MSK) {

		GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK);

		do_IRQ(COBALT_GALILEO_IRQ);



	} else if (pending & GALILEO_INTR_RETRY_CTR) {



		devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8;

		GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS);

		printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n",

	} else if (pending & GT_INTR_RETRYCTR0_MSK) {

		devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8;

		GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK);

		printk(KERN_WARNING

		       "Galileo: PCI retry count exceeded (%02x.%u)\n",

		       PCI_SLOT(devfn), PCI_FUNC(devfn));



	} else {



		GALILEO_OUTL(mask & ~pending, GT_INTRMASK_OFS);

		printk(KERN_WARNING "Galileo: masking unexpected interrupt %08x\n", pending);

		GT_WRITE(GT_INTRMASK_OFS, mask & ~pending);

		printk(KERN_WARNING

		       "Galileo: masking unexpected interrupt %08x\n", pending);

	}

}
@@ -104,7 +101,7 @@ void __init arch_init_irq(void) 
	 * Mask all Galileo interrupts. The Galileo

	 * handler is set in cobalt_timer_setup()

	 */

	GALILEO_OUTL(0, GT_INTRMASK_OFS);

	GT_WRITE(GT_INTRMASK_OFS, 0);



	init_i8259_irqs();				/*  0 ... 15 */

	mips_cpu_irq_init(COBALT_CPU_IRQ);		/* 16 ... 23 */