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Commit c3a2f0df authored by Andrew Vasquez's avatar Andrew Vasquez Committed by James Bottomley
Browse files

[SCSI] qla2xxx: Add ISP25XX support. 



Large code-reuse from ISP24xx, consolidate RISC memory
extraction routines during firmware-dump.

Signed-off-by: default avatarAndrew Vasquez <andrew.vasquez@qlogic.com>
Signed-off-by: default avatarJames Bottomley <James.Bottomley@SteelEye.com>
parent af6177d8

drivers/scsi/qla2xxx/qla_attr.c

+1 −1
Original line number Diff line number Diff line
@@ -206,7 +206,7 @@ static struct bin_attribute sysfs_optrom_attr = { 
		.name = "optrom",

		.mode = S_IRUSR | S_IWUSR,

	},

	.size = OPTROM_SIZE_24XX,

	.size = 0,

	.read = qla2x00_sysfs_read_optrom,

	.write = qla2x00_sysfs_write_optrom,

};

drivers/scsi/qla2xxx/qla_dbg.c

+923 −217

File changed.

Preview size limit exceeded, changes collapsed.

drivers/scsi/qla2xxx/qla_dbg.h

+38 −0
Original line number Diff line number Diff line
@@ -213,6 +213,43 @@ struct qla24xx_fw_dump { 
	uint32_t ext_mem[1];

};



struct qla25xx_fw_dump {

	uint32_t host_status;

	uint32_t host_reg[32];

	uint32_t shadow_reg[11];

	uint32_t risc_io_reg;

	uint16_t mailbox_reg[32];

	uint32_t xseq_gp_reg[128];

	uint32_t xseq_0_reg[48];

	uint32_t xseq_1_reg[16];

	uint32_t rseq_gp_reg[128];

	uint32_t rseq_0_reg[32];

	uint32_t rseq_1_reg[16];

	uint32_t rseq_2_reg[16];

	uint32_t aseq_gp_reg[128];

	uint32_t aseq_0_reg[32];

	uint32_t aseq_1_reg[16];

	uint32_t aseq_2_reg[16];

	uint32_t cmd_dma_reg[16];

	uint32_t req0_dma_reg[15];

	uint32_t resp0_dma_reg[15];

	uint32_t req1_dma_reg[15];

	uint32_t xmt0_dma_reg[32];

	uint32_t xmt1_dma_reg[32];

	uint32_t xmt2_dma_reg[32];

	uint32_t xmt3_dma_reg[32];

	uint32_t xmt4_dma_reg[32];

	uint32_t xmt_data_dma_reg[16];

	uint32_t rcvt0_data_dma_reg[32];

	uint32_t rcvt1_data_dma_reg[32];

	uint32_t risc_gp_reg[128];

	uint32_t lmc_reg[128];

	uint32_t fpm_hdw_reg[192];

	uint32_t fb_hdw_reg[192];

	uint32_t code_ram[0x2000];

	uint32_t ext_mem[1];

};



#define EFT_NUM_BUFFERS		4

#define EFT_BYTES_PER_BUFFER	0x4000

#define EFT_SIZE		((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
@@ -246,5 +283,6 @@ struct qla2xxx_fw_dump { 
		struct qla2100_fw_dump isp21;

		struct qla2300_fw_dump isp23;

		struct qla24xx_fw_dump isp24;

		struct qla25xx_fw_dump isp25;

	} isp;

};

drivers/scsi/qla2xxx/qla_def.h

+7 −1
Original line number Diff line number Diff line
@@ -2209,6 +2209,7 @@ typedef struct scsi_qla_host { 
#define	SWITCH_FOUND			BIT_3

#define	DFLG_NO_CABLE			BIT_4



#define PCI_DEVICE_ID_QLOGIC_ISP2532	0x2532

	uint32_t	device_type;

#define DT_ISP2100			BIT_0

#define DT_ISP2200			BIT_1
@@ -2221,7 +2222,8 @@ typedef struct scsi_qla_host { 
#define DT_ISP2432			BIT_8

#define DT_ISP5422			BIT_9

#define DT_ISP5432			BIT_10

#define DT_ISP_LAST			(DT_ISP5432 << 1)

#define DT_ISP2532			BIT_11

#define DT_ISP_LAST			(DT_ISP2532 << 1)



#define DT_IIDMA			BIT_26

#define DT_FWI2				BIT_27
@@ -2242,11 +2244,13 @@ typedef struct scsi_qla_host { 
#define IS_QLA2432(ha)	(DT_MASK(ha) & DT_ISP2432)

#define IS_QLA5422(ha)	(DT_MASK(ha) & DT_ISP5422)

#define IS_QLA5432(ha)	(DT_MASK(ha) & DT_ISP5432)

#define IS_QLA2532(ha)	(DT_MASK(ha) & DT_ISP2532)



#define IS_QLA23XX(ha)	(IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \

    			 IS_QLA6312(ha) || IS_QLA6322(ha))

#define IS_QLA24XX(ha)	(IS_QLA2422(ha) || IS_QLA2432(ha))

#define IS_QLA54XX(ha)	(IS_QLA5422(ha) || IS_QLA5432(ha))

#define IS_QLA25XX(ha)	(IS_QLA2532(ha))



#define IS_IIDMA_CAPABLE(ha)	((ha)->device_type & DT_IIDMA)

#define IS_FWI2_CAPABLE(ha)	((ha)->device_type & DT_FWI2)
@@ -2310,6 +2314,7 @@ typedef struct scsi_qla_host { 
#define PORT_SPEED_1GB	0x00

#define PORT_SPEED_2GB	0x01

#define PORT_SPEED_4GB	0x03

#define PORT_SPEED_8GB	0x04

	uint16_t	link_data_rate;		/* F/W operating speed */



	uint8_t		current_topology;
@@ -2576,6 +2581,7 @@ typedef struct scsi_qla_host { 
#define OPTROM_SIZE_2300	0x20000

#define OPTROM_SIZE_2322	0x100000

#define OPTROM_SIZE_24XX	0x100000

#define OPTROM_SIZE_25XX	0x200000



#include "qla_gbl.h"

#include "qla_dbg.h"

drivers/scsi/qla2xxx/qla_fw.h

+33 −3
Original line number Diff line number Diff line
@@ -8,14 +8,17 @@ 
#define __QLA_FW_H



#define MBS_CHECKSUM_ERROR	0x4010

#define MBS_INVALID_PRODUCT_KEY	0x4020



/*

 * Firmware Options.

 */

#define FO1_ENABLE_PUREX	BIT_10

#define FO1_DISABLE_LED_CTRL	BIT_6

#define FO1_ENABLE_8016		BIT_0

#define FO2_ENABLE_SEL_CLASS2	BIT_5

#define FO3_NO_ABTS_ON_LINKDOWN	BIT_14

#define FO3_HOLD_STS_IOCB	BIT_12



/*

 * Port Database structure definition for ISP 24xx.
@@ -341,7 +344,9 @@ struct init_cb_24xx { 
	 * BIT 10 = Reserved

	 * BIT 11 = Enable FC-SP Security

	 * BIT 12 = FC Tape Enable

	 * BIT 13-31 = Reserved

	 * BIT 13 = Reserved

	 * BIT 14 = Enable Target PRLI Control

	 * BIT 15-31 = Reserved

	 */

	uint32_t firmware_options_2;
@@ -363,7 +368,8 @@ struct init_cb_24xx { 
	 * BIT 13 = Data Rate bit 0

	 * BIT 14 = Data Rate bit 1

	 * BIT 15 = Data Rate bit 2

	 * BIT 16-31 = Reserved

	 * BIT 16 = Enable 75 ohm Termination Select

	 * BIT 17-31 = Reserved

	 */

	uint32_t firmware_options_3;
@@ -435,6 +441,7 @@ struct cmd_type_7 { 
#define TMF_LUN_RESET		BIT_12

#define TMF_CLEAR_TASK_SET	BIT_10

#define TMF_ABORT_TASK_SET	BIT_9

#define TMF_DSD_LIST_ENABLE	BIT_2

#define TMF_READ_DATA		BIT_1

#define TMF_WRITE_DATA		BIT_0
@@ -589,7 +596,7 @@ struct els_entry_24xx { 
#define EST_SOFI3		(1 << 4)

#define EST_SOFI2		(3 << 4)



	uint32_t rx_xchg_address[2];	/* Receive exchange address. */

	uint32_t rx_xchg_address;	/* Receive exchange address. */

	uint16_t rx_dsd_count;



	uint8_t opcode;
@@ -650,6 +657,7 @@ struct logio_entry_24xx { 


	uint16_t control_flags;		/* Control flags. */

					/* Modifiers. */

#define LCF_INCLUDE_SNS		BIT_10	/* Include SNS (FFFFFC) during LOGO. */

#define LCF_FCP2_OVERRIDE	BIT_9	/* Set/Reset word 3 of PRLI. */

#define LCF_CLASS_2		BIT_8	/* Enable class 2 during PLOGI. */

#define LCF_FREE_NPORT		BIT_7	/* Release NPORT handle after LOGO. */
@@ -779,6 +787,15 @@ struct device_reg_24xx { 
#define FA_RISC_CODE_ADDR	0x20000

#define FA_RISC_CODE_SEGMENTS	2



#define FA_FW_AREA_ADDR		0x40000

#define FA_VPD_NVRAM_ADDR	0x48000

#define FA_FEATURE_ADDR		0x4C000

#define FA_FLASH_DESCR_ADDR	0x50000

#define FA_HW_EVENT_ADDR	0x54000

#define FA_BOOT_LOG_ADDR	0x58000

#define FA_FW_DUMP0_ADDR	0x60000

#define FA_FW_DUMP1_ADDR	0x70000



	uint32_t flash_data;		/* Flash/NVRAM BIOS data. */



	uint32_t ctrl_status;		/* Control/Status. */
@@ -859,10 +876,13 @@ struct device_reg_24xx { 
#define HCCRX_CLR_RISC_INT	0xA0000000



	uint32_t gpiod;			/* GPIO Data register. */



					/* LED update mask. */

#define GPDX_LED_UPDATE_MASK	(BIT_20|BIT_19|BIT_18)

					/* Data update mask. */

#define GPDX_DATA_UPDATE_MASK	(BIT_17|BIT_16)

					/* Data update mask. */

#define GPDX_DATA_UPDATE_2_MASK	(BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)

					/* LED control mask. */

#define GPDX_LED_COLOR_MASK	(BIT_4|BIT_3|BIT_2)

					/* LED bit values. Color names as
@@ -877,6 +897,8 @@ struct device_reg_24xx { 
	uint32_t gpioe;			/* GPIO Enable register. */

					/* Enable update mask. */

#define GPEX_ENABLE_UPDATE_MASK	(BIT_17|BIT_16)

					/* Enable update mask. */

#define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)

					/* Enable. */

#define GPEX_ENABLE		(BIT_1|BIT_0)
@@ -916,6 +938,14 @@ struct device_reg_24xx { 
	uint16_t mailbox29;

	uint16_t mailbox30;

	uint16_t mailbox31;



	uint32_t iobase_window;

	uint32_t unused_4[8];		/* Gap. */

	uint32_t iobase_q;

	uint32_t unused_5[2];		/* Gap. */

	uint32_t iobase_select;

	uint32_t unused_6[2];		/* Gap. */

	uint32_t iobase_sdata;

};



/* MID Support ***************************************************************/