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Commit c2be5bfc authored by Joseph Lo's avatar Joseph Lo Committed by Stephen Warren
Browse files

ARM: tegra: clean up the common assembly macros into sleep.h 



There are some common macros for Tegra low-level assembly code. Clean
up them into one header file and move the definitions that will be
re-used into it as well.

Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent bb603277

arch/arm/mach-tegra/headsmp.S

+1 −5
Original line number Diff line number Diff line
@@ -7,17 +7,13 @@ 


#include "flowctrl.h"

#include "reset.h"

#include "sleep.h"



#define APB_MISC_GP_HIDREV	0x804

#define PMC_SCRATCH41	0x140



#define RESET_DATA(x)	((TEGRA_RESET_##x)*4)



	.macro mov32, reg, val

	movw	\reg, #:lower16:\val

	movt	\reg, #:upper16:\val

	.endm



        .section ".text.head", "ax"

	__CPUINIT

arch/arm/mach-tegra/sleep.S

+1 −32
Original line number Diff line number Diff line
@@ -29,36 +29,5 @@ 
#include <mach/iomap.h>



#include "flowctrl.h"

#include "sleep.h"

#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \

					+ IO_PPSB_VIRT)



/* returns the offset of the flow controller halt register for a cpu */

.macro cpu_to_halt_reg rd, rcpu

	cmp	\rcpu, #0

	subne	\rd, \rcpu, #1

	movne	\rd, \rd, lsl #3

	addne	\rd, \rd, #0x14

	moveq	\rd, #0

.endm



/* returns the offset of the flow controller csr register for a cpu */

.macro cpu_to_csr_reg rd, rcpu

	cmp	\rcpu, #0

	subne	\rd, \rcpu, #1

	movne	\rd, \rd, lsl #3

	addne	\rd, \rd, #0x18

	moveq	\rd, #8

.endm



/* returns the ID of the current processor */

.macro cpu_id, rd

	mrc	p15, 0, \rd, c0, c0, 5

	and	\rd, \rd, #0xF

.endm



/* loads a 32-bit value into a register without a data access */

.macro mov32, reg, val

	movw	\reg, #:lower16:\val

	movt	\reg, #:upper16:\val

.endm

arch/arm/mach-tegra/sleep.h

0 → 100644
+56 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#ifndef __MACH_TEGRA_SLEEP_H

#define __MACH_TEGRA_SLEEP_H



#include <mach/iomap.h>



#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \

					+ IO_PPSB_VIRT)



#ifdef __ASSEMBLY__

/* returns the offset of the flow controller halt register for a cpu */

.macro cpu_to_halt_reg rd, rcpu

	cmp	\rcpu, #0

	subne	\rd, \rcpu, #1

	movne	\rd, \rd, lsl #3

	addne	\rd, \rd, #0x14

	moveq	\rd, #0

.endm



/* returns the offset of the flow controller csr register for a cpu */

.macro cpu_to_csr_reg rd, rcpu

	cmp	\rcpu, #0

	subne	\rd, \rcpu, #1

	movne	\rd, \rd, lsl #3

	addne	\rd, \rd, #0x18

	moveq	\rd, #8

.endm



/* returns the ID of the current processor */

.macro cpu_id, rd

	mrc	p15, 0, \rd, c0, c0, 5

	and	\rd, \rd, #0xF

.endm



/* loads a 32-bit value into a register without a data access */

.macro mov32, reg, val

	movw	\reg, #:lower16:\val

	movt	\reg, #:upper16:\val

.endm

#endif

#endif