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Commit c27b2139 authored by Ramesh V's avatar Ramesh V Committed by Gerrit - the friendly Code Review server
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msm: camera: Disable CSIPHY IRQ after sof freeze 



Issue: CSIPHY IRQ enabled when kernel recivies possible sof freeze
and will not disable if there is no csiphy release call from backend
which inturn leads watchdog bark.

Resolution: Dump the CISPHY IRQ at the time of possible sof freeze
and disable them.

CRs-Fixed: 996571

Change-Id: I3c6040b81c04660d3a0ac7ed707e1f4b22498dbd
Signed-off-by: default avatarRamesh V <ramev@codeaurora.org>
parent 25f64653

drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c

+45 −3
Original line number Diff line number Diff line
@@ -46,7 +46,7 @@ 
#define CSI_3PHASE_HW                               1

#define MAX_LANES                                   4

#define CLOCK_OFFSET                              0x700

#define CSIPHY_SOF_DEBUG_COUNT                      3

#define CSIPHY_SOF_DEBUG_COUNT                      2



#undef CDBG

#define CDBG(fmt, args...) pr_debug(fmt, ##args)
@@ -623,6 +623,47 @@ static int msm_csiphy_lane_config(struct csiphy_device *csiphy_dev, 
	return rc;

}



void msm_csiphy_disable_irq(

	struct csiphy_device *csiphy_dev)

{

	void __iomem *csiphybase;



	csiphybase = csiphy_dev->base;

	msm_camera_io_w(0,

		csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

		mipi_csiphy_3ph_cmn_ctrl11.addr);

	msm_camera_io_w(0,

		csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

		mipi_csiphy_3ph_cmn_ctrl12.addr);

	msm_camera_io_w(0,

		csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

		mipi_csiphy_3ph_cmn_ctrl13.addr);

	msm_camera_io_w(0,

		csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

		mipi_csiphy_3ph_cmn_ctrl14.addr);

	msm_camera_io_w(0,

		csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

		mipi_csiphy_3ph_cmn_ctrl15.addr);

	msm_camera_io_w(0,

		csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

		mipi_csiphy_3ph_cmn_ctrl16.addr);

	msm_camera_io_w(0,

		csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

		mipi_csiphy_3ph_cmn_ctrl17.addr);

	msm_camera_io_w(0,

		csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

		mipi_csiphy_3ph_cmn_ctrl18.addr);

	msm_camera_io_w(0,

		csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

		mipi_csiphy_3ph_cmn_ctrl19.addr);

	msm_camera_io_w(0,

		csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

		mipi_csiphy_3ph_cmn_ctrl20.addr);

	msm_camera_io_w(0,

		csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

		mipi_csiphy_3ph_cmn_ctrl21.addr);

}



static irqreturn_t msm_csiphy_irq(int irq_num, void *data)

{

	uint32_t irq;
@@ -632,9 +673,11 @@ static irqreturn_t msm_csiphy_irq(int irq_num, void *data) 
	if (csiphy_dev->csiphy_sof_debug == SOF_DEBUG_ENABLE) {

		if (csiphy_dev->csiphy_sof_debug_count < CSIPHY_SOF_DEBUG_COUNT)

			csiphy_dev->csiphy_sof_debug_count++;

		else

		else {

			msm_csiphy_disable_irq(csiphy_dev);

			return IRQ_HANDLED;

		}

	}



	for (i = 0; i < csiphy_dev->num_irq_registers; i++) {

		irq = msm_camera_io_r(
@@ -1027,7 +1070,6 @@ static int msm_csiphy_release(struct csiphy_device *csiphy_dev, void *arg) 
			mipi_csiphy_glbl_pwr_cfg_addr);

	}

	if (csiphy_dev->csiphy_sof_debug == SOF_DEBUG_ENABLE) {

		csiphy_dev->csiphy_sof_debug = SOF_DEBUG_DISABLE;

		rc = msm_camera_enable_irq(csiphy_dev->irq, false);

	}