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Commit c2714334 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mvebu' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC updates for Marvell mvebu/kirkwood from Olof Johansson:
 "This is a branch with updates for Marvell's mvebu/kirkwood platforms.
  They came in late-ish, and were heavily interdependent such that it
  didn't make sense to split them up across the cross-platform topic
  branches.  So here they are (for the second release in a row) in a
  branch on their own."

* tag 'mvebu' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (88 commits)
  arm: l2x0: add aurora related properties to OF binding
  arm: mvebu: add Aurora L2 Cache Controller to the DT
  arm: mvebu: add L2 cache support
  dma: mv_xor: fix error handling path
  dma: mv_xor: fix error checking of irq_of_parse_and_map()
  dma: mv_xor: use request_irq() instead of devm_request_irq()
  dma: mv_xor: clear the window override control registers
  arm: mvebu: fix address decoding armada_cfg_base() function
  ARM: mvebu: update defconfig with I2C and RTC support
  ARM: mvebu: Add SATA support for OpenBlocks AX3-4
  ARM: mvebu: Add support for the RTC in OpenBlocks AX3-4
  ARM: mvebu: Add support for I2C on OpenBlocks AX3-4
  ARM: mvebu: Add support for I2C controllers in Armada 370/XP
  arm: mvebu: Add hardware I/O Coherency support
  arm: plat-orion: Add coherency attribute when setup mbus target
  arm: dma mapping: Export a dma ops function arm_dma_set_mask
  arm: mvebu: Add SMP support for Armada XP
  arm: mm: Add support for PJ4B cpu and init routines
  arm: mvebu: Add IPI support via doorbells
  arm: mvebu: Add initial support for power managmement service unit
  ...
parents 0beb5878 5e5d8999

Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt

+9 −3
Original line number Diff line number Diff line
@@ -6,9 +6,15 @@ Required properties: 
- interrupt-controller: Identifies the node as an interrupt controller.

- #interrupt-cells: The number of cells to define the interrupts. Should be 1.

  The cell is the IRQ number



- reg: Should contain PMIC registers location and length. First pair

  for the main interrupt registers, second pair for the per-CPU

  interrupt registers

  interrupt registers. For this last pair, to be compliant with SMP

  support, the "virtual" must be use (For the record, these registers

  automatically map to the interrupt controller registers of the

  current CPU)







Example:
@@ -18,6 +24,6 @@ Example: 
              #address-cells = <1>;

              #size-cells = <1>;

              interrupt-controller;

              reg = <0xd0020000 0x1000>,

                    <0xd0021000 0x1000>;

              reg = <0xd0020a00 0x1d0>,

                    <0xd0021070 0x58>;

        };

Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt

0 → 100644
+20 −0
Original line number Diff line number Diff line 
Power Management Service Unit(PMSU)

-----------------------------------

Available on Marvell SOCs: Armada 370 and Armada XP



Required properties:



- compatible: "marvell,armada-370-xp-pmsu"



- reg: Should contain PMSU registers location and length. First pair

  for the per-CPU SW Reset Control registers, second pair for the

  Power Management Service Unit.



Example:



armada-370-xp-pmsu@d0022000 {

	compatible = "marvell,armada-370-xp-pmsu";

	reg = <0xd0022100 0x430>,

	      <0xd0020800 0x20>;

};

Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt

+1 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ Required properties: 
- compatible: Should be "marvell,armada-370-xp-timer"

- interrupts: Should contain the list of Global Timer interrupts

- reg: Should contain the base address of the Global Timer registers

- clocks: clock driving the timer hardware



Optional properties:

- marvell,timer-25Mhz: Tells whether the Global timer supports the 25

Documentation/devicetree/bindings/arm/coherency-fabric.txt

0 → 100644
+21 −0
Original line number Diff line number Diff line 
Coherency fabric

----------------

Available on Marvell SOCs: Armada 370 and Armada XP



Required properties:



- compatible: "marvell,coherency-fabric"



- reg: Should contain coherency fabric registers location and

  length. First pair for the coherency fabric registers, second pair

  for the per-CPU fabric registers registers.



Example:



coherency-fabric@d0020200 {

	compatible = "marvell,coherency-fabric";

	reg = <0xd0020200 0xb0>,

		<0xd0021810 0x1c>;



};

Documentation/devicetree/bindings/arm/l2cc.txt

+9 −0
Original line number Diff line number Diff line
@@ -10,6 +10,12 @@ Required properties: 
	"arm,pl310-cache"

	"arm,l220-cache"

	"arm,l210-cache"

	"marvell,aurora-system-cache": Marvell Controller designed to be

     compatible with the ARM one, with system cache mode (meaning

     maintenance operations on L1 are broadcasted to the L2 and L2

     performs the same operation).

	"marvell,"aurora-outer-cache: Marvell Controller designed to be

	 compatible with the ARM one with outer cache mode.

- cache-unified : Specifies the cache is a unified cache.

- cache-level : Should be set to 2 for a level 2 cache.

- reg : Physical base address and size of cache controller's memory mapped
@@ -29,6 +35,9 @@ Optional properties: 
  filter. Addresses in the filter window are directed to the M1 port. Other

  addresses will go to the M0 port.

- interrupts : 1 combined interrupt.

- cache-id-part: cache id part number to be used if it is not present

  on hardware

- wt-override: If present then L2 is forced to Write through mode



Example: