Loading arch/arm/boot/dts/qcom/markw/msm8953-overclock-markw.dtsi +422 −8 Original line number Diff line number Diff line Loading @@ -15,16 +15,128 @@ /* dts for overckloc markw (for future)*/ /* for сpu in msm8953.dtsi*/ &soc { clock_cpu: qcom,cpu-clock-8953@b116000 { compatible = "qcom,cpu-clock-8953"; reg = <0xb114000 0x68>, <0xb014000 0x68>, <0xb116000 0x400>, <0xb111050 0x0a>, <0xb011050 0x0a>, <0xb1d1050 0x0a>, <0x00a4124 0x0a>; reg-names = "rcgwr-c0-base", "rcgwr-c1-base", "c0-pll", "c0-mux", "c1-mux", "cci-mux", "efuse"; vdd-mx-supply = <&pm8953_s7_level_ao>; vdd-cl-supply = <&apc_vreg>; clocks = <&clock_gcc clk_xo_a_clk_src>; clock-names = "xo_a"; qcom,num-clusters = <2>; qcom,speed0-bin-v0-cl = < 0 0>, < 652800000 1>, < 806400000 2>, < 1036800000 3>, < 1209600000 4>, < 1401600000 5>, < 1689600000 6>, < 1804800000 7>, < 2016000000 8>, < 2208000000 9>; qcom,speed0-bin-v0-cci = < 0 0>, < 261120000 1>, < 320000000 2>, < 414720000 3>, < 483840000 4>, < 560640000 5>, < 675840000 6>, < 721920000 7>, < 806400000 8>, < 883200000 9>; qcom,speed2-bin-v0-cl = < 0 0>, < 652800000 1>, < 806400000 2>, < 1036800000 3>, < 1209600000 4>, < 1401600000 5>, < 1689600000 6>, < 1804800000 7>, < 2016000000 8>, < 2208000000 9>; qcom,speed2-bin-v0-cci = < 0 0>, < 261120000 1>, < 320000000 2>, < 414720000 3>, < 483840000 4>, < 560640000 5>, < 675840000 6>, < 721920000 7>, < 806400000 8>, < 883200000 9>; qcom,speed7-bin-v0-cl = < 0 0>, < 652800000 1>, < 806400000 2>, < 1036800000 3>, < 1209600000 4>, < 1401600000 5>, < 1689600000 6>, < 1804800000 7>, < 2016000000 8>, < 2208000000 9>; qcom,speed7-bin-v0-cci = < 0 0>, < 261120000 1>, < 320000000 2>, < 414720000 3>, < 483840000 4>, < 560640000 5>, < 675840000 6>, < 721920000 7>, < 806400000 8>, < 883200000 9>; qcom,speed6-bin-v0-cl = < 0 0>, < 652800000 1>, < 806400000 2>, < 1036800000 3>, < 1209600000 4>, < 1401600000 5>, < 1689600000 6>, < 1804800000 7>, < 2016000000 8>, < 2208000000 9>; qcom,speed6-bin-v0-cci = < 0 0>, < 261120000 1>, < 320000000 2>, < 414720000 3>, < 483840000 4>, < 560640000 5>, < 675840000 6>, < 721920000 7>, < 806400000 8>, < 883200000 9>; #clock-cells = <1>; }; devfreq-cpufreq { cpubw-cpufreq { target-dev = <&cpubw>; cpu-to-dev-map = < 652800 2124>, < 806400 2124>, <1036800 3221>, <1209600 5126>, <1401600 5859>, <1689600 6445>, <1804800 7104>, < 1958400 7104>, <2016000 7104>, <2208000 7104>; }; Loading @@ -36,6 +148,308 @@ < 2208000 5859 >; }; }; qcom,msm-thermal { msm_thermal_freq: qcom,vdd-apps-rstr { qcom,vdd-rstr-reg = "vdd-apps"; qcom,levels = <652800 2016000 2208000>; qcom,freq-req; }; }; msm_cpufreq: qcom,msm-cpufreq { qcom,cpufreq-table = < 652800>, < 806400>, <1036800>, <1209600>, <1401600>, <1689600>, <1804800>, <2016000>, <2208000>; }; }; /* for cpu in msm8953-regulator.dtsi*/ &soc { apc_cpr: cpr4-ctrl@b018000 { thread@0 { qcom,cpr-thread-id = <0>; qcom,cpr-consecutive-up = <0>; qcom,cpr-consecutive-down = <2>; qcom,cpr-up-threshold = <2>; qcom,cpr-down-threshold = <1>; apc_vreg: regulator { regulator-name = "apc_corner"; regulator-min-microvolt = <1>; regulator-max-microvolt = <9>; qcom,cpr-fuse-corners = <4>; qcom,cpr-fuse-combos = <64>; qcom,cpr-speed-bins = <8>; qcom,cpr-speed-bin-corners = <9 9 9 9 9 9 9 9>; qcom,cpr-corners = <9 9 9 9 9 9 9 9>; qcom,cpr-corner-fmax-map = <1 2 4 9>; qcom,cpr-voltage-ceiling = <715000>, <765000>, <815000>, <855000>, <860000>, <865000>, <920000>, <1055000>, <1065000>; qcom,cpr-voltage-floor = <500000>, <500000>, <500000>, <500000>, <500000>, <500000>, <500000>, <500000>, <500000>; qcom,cpr-floor-to-ceiling-max-range = < 0 0 0 0 0 0 0 0 0>, <50000 50000 50000 50000 50000 50000 50000 50000 50000>, <50000 50000 50000 50000 50000 50000 50000 50000 50000>, <50000 50000 50000 50000 50000 50000 50000 50000 50000>, <50000 50000 50000 50000 50000 50000 50000 50000 50000>, <50000 50000 50000 50000 50000 50000 50000 50000 50000>, <50000 50000 50000 50000 50000 50000 50000 50000 50000>, <50000 50000 50000 50000 50000 50000 50000 50000 50000>; qcom,cpr-misc-fuse-voltage-adjustment = <0 0 0 0 30000 0 0 0 0>, <0 0 0 0 30000 0 0 0 0>; qcom,mem-acc-voltage = <1 1 1 2 2 2 2 2 2>; qcom,corner-frequencies = <652800000>, <806400000>, <1036800000>, <1209600000>, <1401600000>, <1689600000>, <1804800000>, <2016000000>, <2208000000>; qcom,cpr-open-loop-voltage-fuse-adjustment = /* Speed bin 0; CPR rev 0..7 */ < 0 0 0 0>, < 25000 0 5000 40000>, < 25000 0 5000 40000>, < 25000 0 5000 40000>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 1; CPR rev 0..7 */ < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 2; CPR rev 0..7 */ < 0 0 0 0>, < 25000 0 5000 40000>, < 25000 0 5000 40000>, < 25000 0 5000 40000>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 3; CPR rev 0..7 */ < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 4; CPR rev 0..7 */ < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 5; CPR rev 0..7 */ < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 6; CPR rev 0..7 */ < 0 0 0 0>, < 25000 0 5000 40000>, < 25000 0 5000 40000>, < 25000 0 5000 40000>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 7; CPR rev 0..7 */ < 0 0 0 0>, < 25000 0 5000 40000>, < 25000 0 5000 40000>, < 25000 0 5000 40000>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>; qcom,cpr-closed-loop-voltage-fuse-adjustment = /* Speed bin 0; CPR rev 0..7 */ < 0 0 0 0>, < 10000 (-15000) 0 25000>, < 10000 (-15000) 0 25000>, <(-5000) (-30000) (-15000) 10000>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 1; CPR rev 0..7 */ < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 2; CPR rev 0..7 */ < 0 0 0 0>, < 10000 (-15000) 0 25000>, < 10000 (-15000) 0 25000>, <(-5000) (-30000) (-15000) 10000>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 3; CPR rev 0..7 */ < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 4; CPR rev 0..7 */ < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 5; CPR rev 0..7 */ < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 6; CPR rev 0..7 */ < 0 0 0 0>, < 10000 (-15000) 0 25000>, < 10000 (-15000) 0 25000>, <(-5000) (-30000) (-15000) 10000>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 7; CPR rev 0..7 */ < 0 0 0 0>, < 10000 (-15000) 0 25000>, < 10000 (-15000) 0 25000>, <(-5000) (-30000) (-15000) 10000>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>; qcom,cpr-ro-scaling-factor = <3610 3790 0 2200 2450 2310 2170 2210 2330 2210 2470 2340 780 2700 2450 2090>, <3610 3790 0 2200 2450 2310 2170 2210 2330 2210 2470 2340 780 2700 2450 2090>, <3610 3790 0 2200 2450 2310 2170 2210 2330 2210 2470 2340 780 2700 2450 2090>, <3610 3790 0 2200 2450 2310 2170 2210 2330 2210 2470 2340 780 2700 2450 2090>; qcom,allow-voltage-interpolation; qcom,allow-quotient-interpolation; qcom,cpr-scaled-open-loop-voltage-as-ceiling; qcom,corner-allow-temp-adjustment = <0 0 0 0 0 0 0 0 0>, <0 0 0 0 0 0 0 0 0>, <0 0 0 0 0 0 0 0 0>, <1 1 1 1 0 0 0 0 0>, <1 1 1 1 0 0 0 0 0>, <1 1 1 1 0 0 0 0 0>, <1 1 1 1 0 0 0 0 0>, <1 1 1 1 0 0 0 0 0>; qcom,cpr-corner1-temp-core-voltage-adjustment = <(0) (-5000) (-15000) (-20000)>; qcom,cpr-corner2-temp-core-voltage-adjustment = <(0) (-5000) (-15000) (-15000)>; qcom,cpr-corner3-temp-core-voltage-adjustment = <(0) (-5000) (-15000) (-10000)>; qcom,cpr-corner4-temp-core-voltage-adjustment = <(0) (-5000) (-15000) (0)>; qcom,cpr-aging-max-voltage-adjustment = <15000>; qcom,cpr-aging-ref-corner = <6>; /* Turbo */ qcom,cpr-aging-ro-scaling-factor = <2800>; qcom,allow-aging-voltage-adjustment = <0 0 0 1 1 1 1 1>; }; }; }; }; /* msm8953-gpu.dtsi */ Loading Loading
arch/arm/boot/dts/qcom/markw/msm8953-overclock-markw.dtsi +422 −8 Original line number Diff line number Diff line Loading @@ -15,16 +15,128 @@ /* dts for overckloc markw (for future)*/ /* for сpu in msm8953.dtsi*/ &soc { clock_cpu: qcom,cpu-clock-8953@b116000 { compatible = "qcom,cpu-clock-8953"; reg = <0xb114000 0x68>, <0xb014000 0x68>, <0xb116000 0x400>, <0xb111050 0x0a>, <0xb011050 0x0a>, <0xb1d1050 0x0a>, <0x00a4124 0x0a>; reg-names = "rcgwr-c0-base", "rcgwr-c1-base", "c0-pll", "c0-mux", "c1-mux", "cci-mux", "efuse"; vdd-mx-supply = <&pm8953_s7_level_ao>; vdd-cl-supply = <&apc_vreg>; clocks = <&clock_gcc clk_xo_a_clk_src>; clock-names = "xo_a"; qcom,num-clusters = <2>; qcom,speed0-bin-v0-cl = < 0 0>, < 652800000 1>, < 806400000 2>, < 1036800000 3>, < 1209600000 4>, < 1401600000 5>, < 1689600000 6>, < 1804800000 7>, < 2016000000 8>, < 2208000000 9>; qcom,speed0-bin-v0-cci = < 0 0>, < 261120000 1>, < 320000000 2>, < 414720000 3>, < 483840000 4>, < 560640000 5>, < 675840000 6>, < 721920000 7>, < 806400000 8>, < 883200000 9>; qcom,speed2-bin-v0-cl = < 0 0>, < 652800000 1>, < 806400000 2>, < 1036800000 3>, < 1209600000 4>, < 1401600000 5>, < 1689600000 6>, < 1804800000 7>, < 2016000000 8>, < 2208000000 9>; qcom,speed2-bin-v0-cci = < 0 0>, < 261120000 1>, < 320000000 2>, < 414720000 3>, < 483840000 4>, < 560640000 5>, < 675840000 6>, < 721920000 7>, < 806400000 8>, < 883200000 9>; qcom,speed7-bin-v0-cl = < 0 0>, < 652800000 1>, < 806400000 2>, < 1036800000 3>, < 1209600000 4>, < 1401600000 5>, < 1689600000 6>, < 1804800000 7>, < 2016000000 8>, < 2208000000 9>; qcom,speed7-bin-v0-cci = < 0 0>, < 261120000 1>, < 320000000 2>, < 414720000 3>, < 483840000 4>, < 560640000 5>, < 675840000 6>, < 721920000 7>, < 806400000 8>, < 883200000 9>; qcom,speed6-bin-v0-cl = < 0 0>, < 652800000 1>, < 806400000 2>, < 1036800000 3>, < 1209600000 4>, < 1401600000 5>, < 1689600000 6>, < 1804800000 7>, < 2016000000 8>, < 2208000000 9>; qcom,speed6-bin-v0-cci = < 0 0>, < 261120000 1>, < 320000000 2>, < 414720000 3>, < 483840000 4>, < 560640000 5>, < 675840000 6>, < 721920000 7>, < 806400000 8>, < 883200000 9>; #clock-cells = <1>; }; devfreq-cpufreq { cpubw-cpufreq { target-dev = <&cpubw>; cpu-to-dev-map = < 652800 2124>, < 806400 2124>, <1036800 3221>, <1209600 5126>, <1401600 5859>, <1689600 6445>, <1804800 7104>, < 1958400 7104>, <2016000 7104>, <2208000 7104>; }; Loading @@ -36,6 +148,308 @@ < 2208000 5859 >; }; }; qcom,msm-thermal { msm_thermal_freq: qcom,vdd-apps-rstr { qcom,vdd-rstr-reg = "vdd-apps"; qcom,levels = <652800 2016000 2208000>; qcom,freq-req; }; }; msm_cpufreq: qcom,msm-cpufreq { qcom,cpufreq-table = < 652800>, < 806400>, <1036800>, <1209600>, <1401600>, <1689600>, <1804800>, <2016000>, <2208000>; }; }; /* for cpu in msm8953-regulator.dtsi*/ &soc { apc_cpr: cpr4-ctrl@b018000 { thread@0 { qcom,cpr-thread-id = <0>; qcom,cpr-consecutive-up = <0>; qcom,cpr-consecutive-down = <2>; qcom,cpr-up-threshold = <2>; qcom,cpr-down-threshold = <1>; apc_vreg: regulator { regulator-name = "apc_corner"; regulator-min-microvolt = <1>; regulator-max-microvolt = <9>; qcom,cpr-fuse-corners = <4>; qcom,cpr-fuse-combos = <64>; qcom,cpr-speed-bins = <8>; qcom,cpr-speed-bin-corners = <9 9 9 9 9 9 9 9>; qcom,cpr-corners = <9 9 9 9 9 9 9 9>; qcom,cpr-corner-fmax-map = <1 2 4 9>; qcom,cpr-voltage-ceiling = <715000>, <765000>, <815000>, <855000>, <860000>, <865000>, <920000>, <1055000>, <1065000>; qcom,cpr-voltage-floor = <500000>, <500000>, <500000>, <500000>, <500000>, <500000>, <500000>, <500000>, <500000>; qcom,cpr-floor-to-ceiling-max-range = < 0 0 0 0 0 0 0 0 0>, <50000 50000 50000 50000 50000 50000 50000 50000 50000>, <50000 50000 50000 50000 50000 50000 50000 50000 50000>, <50000 50000 50000 50000 50000 50000 50000 50000 50000>, <50000 50000 50000 50000 50000 50000 50000 50000 50000>, <50000 50000 50000 50000 50000 50000 50000 50000 50000>, <50000 50000 50000 50000 50000 50000 50000 50000 50000>, <50000 50000 50000 50000 50000 50000 50000 50000 50000>; qcom,cpr-misc-fuse-voltage-adjustment = <0 0 0 0 30000 0 0 0 0>, <0 0 0 0 30000 0 0 0 0>; qcom,mem-acc-voltage = <1 1 1 2 2 2 2 2 2>; qcom,corner-frequencies = <652800000>, <806400000>, <1036800000>, <1209600000>, <1401600000>, <1689600000>, <1804800000>, <2016000000>, <2208000000>; qcom,cpr-open-loop-voltage-fuse-adjustment = /* Speed bin 0; CPR rev 0..7 */ < 0 0 0 0>, < 25000 0 5000 40000>, < 25000 0 5000 40000>, < 25000 0 5000 40000>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 1; CPR rev 0..7 */ < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 2; CPR rev 0..7 */ < 0 0 0 0>, < 25000 0 5000 40000>, < 25000 0 5000 40000>, < 25000 0 5000 40000>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 3; CPR rev 0..7 */ < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 4; CPR rev 0..7 */ < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 5; CPR rev 0..7 */ < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 6; CPR rev 0..7 */ < 0 0 0 0>, < 25000 0 5000 40000>, < 25000 0 5000 40000>, < 25000 0 5000 40000>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 7; CPR rev 0..7 */ < 0 0 0 0>, < 25000 0 5000 40000>, < 25000 0 5000 40000>, < 25000 0 5000 40000>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>; qcom,cpr-closed-loop-voltage-fuse-adjustment = /* Speed bin 0; CPR rev 0..7 */ < 0 0 0 0>, < 10000 (-15000) 0 25000>, < 10000 (-15000) 0 25000>, <(-5000) (-30000) (-15000) 10000>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 1; CPR rev 0..7 */ < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 2; CPR rev 0..7 */ < 0 0 0 0>, < 10000 (-15000) 0 25000>, < 10000 (-15000) 0 25000>, <(-5000) (-30000) (-15000) 10000>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 3; CPR rev 0..7 */ < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 4; CPR rev 0..7 */ < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 5; CPR rev 0..7 */ < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 6; CPR rev 0..7 */ < 0 0 0 0>, < 10000 (-15000) 0 25000>, < 10000 (-15000) 0 25000>, <(-5000) (-30000) (-15000) 10000>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, /* Speed bin 7; CPR rev 0..7 */ < 0 0 0 0>, < 10000 (-15000) 0 25000>, < 10000 (-15000) 0 25000>, <(-5000) (-30000) (-15000) 10000>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>, < 0 0 0 0>; qcom,cpr-ro-scaling-factor = <3610 3790 0 2200 2450 2310 2170 2210 2330 2210 2470 2340 780 2700 2450 2090>, <3610 3790 0 2200 2450 2310 2170 2210 2330 2210 2470 2340 780 2700 2450 2090>, <3610 3790 0 2200 2450 2310 2170 2210 2330 2210 2470 2340 780 2700 2450 2090>, <3610 3790 0 2200 2450 2310 2170 2210 2330 2210 2470 2340 780 2700 2450 2090>; qcom,allow-voltage-interpolation; qcom,allow-quotient-interpolation; qcom,cpr-scaled-open-loop-voltage-as-ceiling; qcom,corner-allow-temp-adjustment = <0 0 0 0 0 0 0 0 0>, <0 0 0 0 0 0 0 0 0>, <0 0 0 0 0 0 0 0 0>, <1 1 1 1 0 0 0 0 0>, <1 1 1 1 0 0 0 0 0>, <1 1 1 1 0 0 0 0 0>, <1 1 1 1 0 0 0 0 0>, <1 1 1 1 0 0 0 0 0>; qcom,cpr-corner1-temp-core-voltage-adjustment = <(0) (-5000) (-15000) (-20000)>; qcom,cpr-corner2-temp-core-voltage-adjustment = <(0) (-5000) (-15000) (-15000)>; qcom,cpr-corner3-temp-core-voltage-adjustment = <(0) (-5000) (-15000) (-10000)>; qcom,cpr-corner4-temp-core-voltage-adjustment = <(0) (-5000) (-15000) (0)>; qcom,cpr-aging-max-voltage-adjustment = <15000>; qcom,cpr-aging-ref-corner = <6>; /* Turbo */ qcom,cpr-aging-ro-scaling-factor = <2800>; qcom,allow-aging-voltage-adjustment = <0 0 0 1 1 1 1 1>; }; }; }; }; /* msm8953-gpu.dtsi */ Loading