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Commit c1dbed58 authored by Amir Levy's avatar Amir Levy
Browse files

msm: ipa3: disable TX prefetch to support MBIM 



In order to enable MBIM aggregation TX prefetch needs to be disabled.
Disable TX prefetch on boot when non MHI configuration is detected.

CRs-Fixed: 1097871
Change-Id: I4107f3e54293421b9b4fdbcb62a09528bb6b775c
Acked-by: default avatarAdy Abraham <adya@qti.qualcomm.com>
Signed-off-by: default avatarSkylar Chang <chiaweic@codeaurora.org>
Signed-off-by: default avatarAmir Levy <alevy@codeaurora.org>
parent 9b1e836e

drivers/platform/msm/ipa/ipa_v3/ipa.c

+7 −0
Original line number Original line Diff line number Diff line
@@ -4010,6 +4010,13 @@ static int ipa3_post_init(const struct ipa3_plat_drv_res *resource_p, 
		IPADBG("Initialization of ipa interrupts skipped\n");

		IPADBG("Initialization of ipa interrupts skipped\n");

	}

	}





	/*

	 * IPAv3.5.x requires to disable prefetch for USB in order to allow

	 * MBIM to work, currently MBIM is not needed in MHI mode.

	 */

	if (!ipa3_ctx->ipa_config_is_mhi)

		ipa3_disable_prefetch(IPA_CLIENT_USB_CONS);



	if (ipa3_ctx->transport_prototype == IPA_TRANSPORT_TYPE_GSI) {

	if (ipa3_ctx->transport_prototype == IPA_TRANSPORT_TYPE_GSI) {

		memset(&gsi_props, 0, sizeof(gsi_props));

		memset(&gsi_props, 0, sizeof(gsi_props));

		gsi_props.ver = ipa3_get_gsi_ver(resource_p->ipa_hw_type);

		gsi_props.ver = ipa3_get_gsi_ver(resource_p->ipa_hw_type);

drivers/platform/msm/ipa/ipa_v3/ipa_i.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -2020,4 +2020,5 @@ bool ipa3_is_msm_device(void); 
int ipa3_tz_unlock_reg(struct ipa_tz_unlock_reg_info *reg_info, u16 num_regs);

int ipa3_tz_unlock_reg(struct ipa_tz_unlock_reg_info *reg_info, u16 num_regs);

struct device *ipa3_get_pdev(void);

struct device *ipa3_get_pdev(void);

void ipa3_enable_dcd(void);

void ipa3_enable_dcd(void);

void ipa3_disable_prefetch(enum ipa_client_type client);

#endif /* _IPA3_I_H_ */
 
#endif /* _IPA3_I_H_ */

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

+27 −0
Original line number Original line Diff line number Diff line
@@ -6207,6 +6207,33 @@ bool ipa3_is_msm_device(void) 
	return false;

	return false;

}

}





/**

* ipa3_disable_prefetch() - disable\enable tx prefetch

*

* @client: the client which is related to the TX where prefetch will be

*          disabled

*

* Return value: Non applicable

*

*/

void ipa3_disable_prefetch(enum ipa_client_type client)

{

	struct ipahal_reg_tx_cfg cfg;

	u8 qmb;



	qmb = ipa3_get_qmb_master_sel(client);



	IPADBG("disabling prefetch for qmb %d\n", (int)qmb);



	ipahal_read_reg_fields(IPA_TX_CFG, &cfg);

	/* QMB0 (DDR) correlates with TX0, QMB1(PCIE) correlates with TX1 */

	if (qmb == QMB_MASTER_SELECT_DDR)

		cfg.tx0_prefetch_disable = true;

	else

		cfg.tx1_prefetch_disable = true;

	ipahal_write_reg_fields(IPA_TX_CFG, &cfg);

}



/**

/**

 * ipa3_get_pdev() - return a pointer to IPA dev struct

 * ipa3_get_pdev() - return a pointer to IPA dev struct

 *

 *

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c

+22 −2
Original line number Original line Diff line number Diff line 
/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.

/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.

 *

 *

 * This program is free software; you can redistribute it and/or modify

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * it under the terms of the GNU General Public License version 2 and
@@ -889,6 +889,26 @@ static void ipareg_construct_qsb_max_reads(enum ipahal_reg_name reg, 
			    IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BMSK);

			    IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BMSK);

}

}





static void ipareg_parse_tx_cfg(enum ipahal_reg_name reg,

	void *fields, u32 val)

{

	struct ipahal_reg_tx_cfg *tx_cfg;



	tx_cfg = (struct ipahal_reg_tx_cfg *)fields;



	tx_cfg->tx0_prefetch_disable = IPA_GETFIELD_FROM_REG(val,

		IPA_TX_CFG_TX0_PREFETCH_DISABLE_SHFT_V3_5,

		IPA_TX_CFG_TX0_PREFETCH_DISABLE_BMSK_V3_5);



	tx_cfg->tx1_prefetch_disable = IPA_GETFIELD_FROM_REG(val,

		IPA_TX_CFG_TX1_PREFETCH_DISABLE_SHFT_V3_5,

		IPA_TX_CFG_TX1_PREFETCH_DISABLE_BMSK_V3_5);



	tx_cfg->prefetch_almost_empty_size = IPA_GETFIELD_FROM_REG(val,

		IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_SHFT_V3_5,

		IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_BMSK_V3_5);

}



static void ipareg_construct_tx_cfg(enum ipahal_reg_name reg,

static void ipareg_construct_tx_cfg(enum ipahal_reg_name reg,

	const void *fields, u32 *val)

	const void *fields, u32 *val)

{

{
@@ -1153,7 +1173,7 @@ static struct ipahal_reg_obj ipahal_reg_objs[IPA_HW_MAX][IPA_REG_MAX] = { 




	/* IPAv3.5 */

	/* IPAv3.5 */

	[IPA_HW_v3_5][IPA_TX_CFG] = {

	[IPA_HW_v3_5][IPA_TX_CFG] = {

		ipareg_construct_tx_cfg, ipareg_parse_dummy,

		ipareg_construct_tx_cfg, ipareg_parse_tx_cfg,

		0x000001FC, 0},

		0x000001FC, 0},

	[IPA_HW_v3_5][IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n] = {

	[IPA_HW_v3_5][IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n] = {

		ipareg_construct_rsrg_grp_xy_v3_5, ipareg_parse_dummy,

		ipareg_construct_rsrg_grp_xy_v3_5, ipareg_parse_dummy,