Commit c1d98e1e authored Oct 07, 2015 by Devesh Jhunjhunwala

clk: msm: clock-gcc-californium: Update pcie_aux_clk_src freq_table



The gcc_pcie_sleep_clk needs to runs at 19.2 MHz, so update
the frequency table of the parent rcg to allow this.

CRs-Fixed: 920470
Change-Id: Iac8c305b0291dcb7cbbb85e4101bf41a1065e79e
Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>

parent bb29ea15

drivers/clk/msm/clock-gcc-californium.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -633,6 +633,7 @@ static struct rcg_clk gp3_clk_src = {

		static struct clk_freq_tbl ftbl_pcie_aux_clk_src[] = {
		F( 1000000, xo, 1, 5, 96),
		F( 19200000, xo, 1, 0, 0),
		F_END
		};