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Commit c1003d9c authored by Francisco Jerez's avatar Francisco Jerez Committed by Ben Skeggs
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drm/nv17-nv40: Fix modesetting failure when pitch == 4096px (fdo bug 35901). 



Reported-by: default avatarMario Bachmann <grafgrimm77@gmx.de>
Tested-by: default avatarGreg Turner <gmturner007@ameritech.net>
Signed-off-by: default avatarFrancisco Jerez <currojerez@riseup.net>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 18b54c4d

drivers/gpu/drm/nouveau/nouveau_hw.c

+2 −0
Original line number Diff line number Diff line
@@ -900,6 +900,7 @@ nv_save_state_ext(struct drm_device *dev, int head, 
	}

	/* NV11 and NV20 don't have this, they stop at 0x52. */

	if (nv_gf4_disp_arch(dev)) {

		rd_cio_state(dev, head, regp, NV_CIO_CRE_42);

		rd_cio_state(dev, head, regp, NV_CIO_CRE_53);

		rd_cio_state(dev, head, regp, NV_CIO_CRE_54);
@@ -1003,6 +1004,7 @@ nv_load_state_ext(struct drm_device *dev, int head, 
			nouveau_wait_eq(dev, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0);

		}



		wr_cio_state(dev, head, regp, NV_CIO_CRE_42);

		wr_cio_state(dev, head, regp, NV_CIO_CRE_53);

		wr_cio_state(dev, head, regp, NV_CIO_CRE_54);

drivers/gpu/drm/nouveau/nv04_crtc.c

+7 −1
Original line number Diff line number Diff line
@@ -376,7 +376,10 @@ nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode) 
	 */



	/* framebuffer can be larger than crtc scanout area. */

	regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = XLATE(fb->pitch / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);

	regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =

		XLATE(fb->pitch / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);

	regp->CRTC[NV_CIO_CRE_42] =

		XLATE(fb->pitch / 8, 11, NV_CIO_CRE_42_OFFSET_11);

	regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?

					    MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00;

	regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) |
@@ -824,8 +827,11 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, 
	regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitch >> 3;

	regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =

		XLATE(drm_fb->pitch >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);

	regp->CRTC[NV_CIO_CRE_42] =

		XLATE(drm_fb->pitch / 8, 11, NV_CIO_CRE_42_OFFSET_11);

	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);

	crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX);

	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42);



	/* Update the framebuffer location. */

	regp->fb_start = nv_crtc->fb.offset & ~3;

drivers/gpu/drm/nouveau/nvreg.h

+2 −0
Original line number Diff line number Diff line
@@ -277,6 +277,8 @@ 
#		define NV_CIO_CRE_EBR_VDE_11		2:2

#		define NV_CIO_CRE_EBR_VRS_11		4:4

#		define NV_CIO_CRE_EBR_VBS_11		6:6

#	define NV_CIO_CRE_42			0x42

#		define NV_CIO_CRE_42_OFFSET_11		6:6

#	define NV_CIO_CRE_43			0x43

#	define NV_CIO_CRE_44			0x44	/* head control */

#	define NV_CIO_CRE_CSB			0x45	/* colour saturation boost */