[PATCH] ARM: 2693/1: Add PCI support for Versatile/PB (c0da085a) · Commits · e / devices / android_kernel_xiaomi_markw

arch/arm/Kconfig

+1 −1

Original line number	Diff line number	Diff line
		@@ -280,7 +280,7 @@ config ISA_DMA_API
		default y

		config PCI
		bool "PCI support" if ARCH_INTEGRATOR_AP
		bool "PCI support" if ARCH_INTEGRATOR_AP \|\| ARCH_VERSATILE_PB
		help
		Find out whether you have a PCI motherboard. PCI is the name of a
		bus system, i.e. the way the CPU talks to the other stuff inside

arch/arm/mach-versatile/Makefile

+1 −0

Original line number	Diff line number	Diff line
		@@ -5,3 +5,4 @@
		obj-y := core.o clock.o
		obj-$(CONFIG_ARCH_VERSATILE_PB) += versatile_pb.o
		obj-$(CONFIG_MACH_VERSATILE_AB) += versatile_ab.o
		obj-$(CONFIG_PCI) += pci.o

arch/arm/mach-versatile/core.c

+9 −5

Original line number	Diff line number	Diff line
		@@ -196,11 +196,15 @@ static struct map_desc versatile_io_desc[] __initdata = {
		#ifdef CONFIG_DEBUG_LL
		{ IO_ADDRESS(VERSATILE_UART0_BASE), VERSATILE_UART0_BASE, SZ_4K, MT_DEVICE },
		#endif
		#ifdef FIXME
		{ PCI_MEMORY_VADDR, PHYS_PCI_MEM_BASE, SZ_16M, MT_DEVICE },
		{ PCI_CONFIG_VADDR, PHYS_PCI_CONFIG_BASE, SZ_16M, MT_DEVICE },
		{ PCI_V3_VADDR, PHYS_PCI_V3_BASE, SZ_512K, MT_DEVICE },
		{ PCI_IO_VADDR, PHYS_PCI_IO_BASE, SZ_64K, MT_DEVICE },
		#ifdef CONFIG_PCI
		{ IO_ADDRESS(VERSATILE_PCI_CORE_BASE), VERSATILE_PCI_CORE_BASE, SZ_4K, MT_DEVICE },
		{ VERSATILE_PCI_VIRT_BASE, VERSATILE_PCI_BASE, VERSATILE_PCI_BASE_SIZE, MT_DEVICE },
		{ VERSATILE_PCI_CFG_VIRT_BASE, VERSATILE_PCI_CFG_BASE, VERSATILE_PCI_CFG_BASE_SIZE, MT_DEVICE },
		#if 0
		{ VERSATILE_PCI_VIRT_MEM_BASE0, VERSATILE_PCI_MEM_BASE0, SZ_16M, MT_DEVICE },
		{ VERSATILE_PCI_VIRT_MEM_BASE1, VERSATILE_PCI_MEM_BASE1, SZ_16M, MT_DEVICE },
		{ VERSATILE_PCI_VIRT_MEM_BASE2, VERSATILE_PCI_MEM_BASE2, SZ_16M, MT_DEVICE },
		#endif
		#endif
		};

arch/arm/mach-versatile/pci.c

0 → 100644

+360 −0

Original line number	Diff line number	Diff line
		/*
		* linux/arch/arm/mach-versatile/pci.c
		*
		* (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved.
		* You can redistribute and/or modify this software under the terms of version 2
		* of the GNU General Public License as published by the Free Software Foundation.
		* THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
		* WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
		* General Public License for more details.
		* Koninklijke Philips Electronics nor its subsidiaries is obligated to provide any support for this software.
		*
		* ARM Versatile PCI driver.
		*
		* 14/04/2005 Initial version, colin.king@philips.com
		*
		*/
		#include <linux/config.h>
		#include <linux/kernel.h>
		#include <linux/pci.h>
		#include <linux/ptrace.h>
		#include <linux/slab.h>
		#include <linux/ioport.h>
		#include <linux/interrupt.h>
		#include <linux/spinlock.h>
		#include <linux/init.h>

		#include <asm/hardware.h>
		#include <asm/io.h>
		#include <asm/irq.h>
		#include <asm/system.h>
		#include <asm/mach/pci.h>
		#include <asm/mach-types.h>

		/*
		* these spaces are mapped using the following base registers:
		*
		* Usage Local Bus Memory Base/Map registers used
		*
		* Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0, non prefetch
		* Mem 60000000 - 6FFFFFFF LB_BASE1/LB_MAP1, prefetch
		* IO 44000000 - 4FFFFFFF LB_BASE2/LB_MAP2, IO
		* Cfg 42000000 - 42FFFFFF PCI config
		*
		*/
		#define SYS_PCICTL IO_ADDRESS(VERSATILE_SYS_PCICTL)
		#define PCI_IMAP0 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
		#define PCI_IMAP1 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
		#define PCI_IMAP2 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
		#define PCI_SMAP0 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x10)
		#define PCI_SMAP1 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
		#define PCI_SMAP2 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
		#define PCI_SELFID IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)

		#define DEVICE_ID_OFFSET 0x00
		#define CSR_OFFSET 0x04
		#define CLASS_ID_OFFSET 0x08

		#define VP_PCI_DEVICE_ID 0x030010ee
		#define VP_PCI_CLASS_ID 0x0b400000

		static unsigned long pci_slot_ignore = 0;

		static int __init versatile_pci_slot_ignore(char *str)
		{
		int retval;
		int slot;

		while ((retval = get_option(&str,&slot))) {
		if ((slot < 0) \|\| (slot > 31)) {
		printk("Illegal slot value: %d\n",slot);
		} else {
		pci_slot_ignore \|= (1 << slot);
		}
		}
		return 1;
		}

		__setup("pci_slot_ignore=", versatile_pci_slot_ignore);


		static unsigned long __pci_addr(struct pci_bus *bus,
		unsigned int devfn, int offset)
		{
		unsigned int busnr = bus->number;

		/*
		* Trap out illegal values
		*/
		if (offset > 255)
		BUG();
		if (busnr > 255)
		BUG();
		if (devfn > 255)
		BUG();

		return (VERSATILE_PCI_CFG_VIRT_BASE \| (busnr << 16) \|
		(PCI_SLOT(devfn) << 11) \| (PCI_FUNC(devfn) << 8) \| offset);
		}

		static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where,
		int size, u32 *val)
		{
		unsigned long addr = __pci_addr(bus, devfn, where);
		u32 v;
		int slot = PCI_SLOT(devfn);

		if (pci_slot_ignore & (1 << slot)) {
		/* Ignore this slot */
		switch (size) {
		case 1:
		v = 0xff;
		break;
		case 2:
		v = 0xffff;
		break;
		default:
		v = 0xffffffff;
		}
		} else {
		switch (size) {
		case 1:
		addr &= ~3;
		v = __raw_readb(addr);
		break;

		case 2:
		v = __raw_readl(addr & ~3);
		if (addr & 2) v >>= 16;
		v &= 0xffff;
		break;

		default:
		addr &= ~3;
		v = __raw_readl(addr);
		break;
		}
		}

		*val = v;
		return PCIBIOS_SUCCESSFUL;
		}

		static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where,
		int size, u32 val)
		{
		unsigned long addr = __pci_addr(bus, devfn, where);
		int slot = PCI_SLOT(devfn);

		if (pci_slot_ignore & (1 << slot)) {
		return PCIBIOS_SUCCESSFUL;
		}

		switch (size) {
		case 1:
		__raw_writeb((u8)val, addr);
		break;

		case 2:
		__raw_writew((u16)val, addr);
		break;

		case 4:
		__raw_writel(val, addr);
		break;
		}

		return PCIBIOS_SUCCESSFUL;
		}

		static struct pci_ops pci_versatile_ops = {
		.read = versatile_read_config,
		.write = versatile_write_config,
		};

		static struct resource io_mem = {
		.name = "PCI I/O space",
		.start = VERSATILE_PCI_MEM_BASE0,
		.end = VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
		.flags = IORESOURCE_IO,
		};

		static struct resource non_mem = {
		.name = "PCI non-prefetchable",
		.start = VERSATILE_PCI_MEM_BASE1,
		.end = VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
		.flags = IORESOURCE_MEM,
		};

		static struct resource pre_mem = {
		.name = "PCI prefetchable",
		.start = VERSATILE_PCI_MEM_BASE2,
		.end = VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
		.flags = IORESOURCE_MEM \| IORESOURCE_PREFETCH,
		};

		static int __init pci_versatile_setup_resources(struct resource **resource)
		{
		int ret = 0;

		ret = request_resource(&iomem_resource, &io_mem);
		if (ret) {
		printk(KERN_ERR "PCI: unable to allocate I/O "
		"memory region (%d)\n", ret);
		goto out;
		}
		ret = request_resource(&iomem_resource, &non_mem);
		if (ret) {
		printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
		"memory region (%d)\n", ret);
		goto release_io_mem;
		}
		ret = request_resource(&iomem_resource, &pre_mem);
		if (ret) {
		printk(KERN_ERR "PCI: unable to allocate prefetchable "
		"memory region (%d)\n", ret);
		goto release_non_mem;
		}

		/*
		* bus->resource[0] is the IO resource for this bus
		* bus->resource[1] is the mem resource for this bus
		* bus->resource[2] is the prefetch mem resource for this bus
		*/
		resource[0] = &io_mem;
		resource[1] = &non_mem;
		resource[2] = &pre_mem;

		goto out;

		release_non_mem:
		release_resource(&non_mem);
		release_io_mem:
		release_resource(&io_mem);
		out:
		return ret;
		}

		int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
		{
		int ret = 0;
		int i;
		int myslot = -1;
		unsigned long val;

		if (nr == 0) {
		sys->mem_offset = 0;
		ret = pci_versatile_setup_resources(sys->resource);
		if (ret < 0) {
		printk("pci_versatile_setup: resources... oops?\n");
		goto out;
		}
		} else {
		printk("pci_versatile_setup: resources... nr == 0??\n");
		goto out;
		}

		__raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28,PCI_IMAP0);
		__raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28,PCI_IMAP1);
		__raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28,PCI_IMAP2);

		__raw_writel(1, SYS_PCICTL);

		val = __raw_readl(SYS_PCICTL);
		if (!(val & 1)) {
		printk("Not plugged into PCI backplane!\n");
		ret = -EIO;
		goto out;
		}

		/*
		* We need to discover the PCI core first to configure itself
		* before the main PCI probing is performed
		*/
		for (i=0; i<32; i++) {
		if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
		(__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
		myslot = i;

		__raw_writel(myslot, PCI_SELFID);
		val = __raw_readl(VERSATILE_PCI_CFG_VIRT_BASE+(myslot<<11)+CSR_OFFSET);
		val \|= (1<<2);
		__raw_writel(val, VERSATILE_PCI_CFG_VIRT_BASE+(myslot<<11)+CSR_OFFSET);
		break;
		}
		}

		if (myslot == -1) {
		printk("Cannot find PCI core!\n");
		ret = -EIO;
		} else {
		printk("PCI core found (slot %d)\n",myslot);
		/* Do not to map Versatile FPGA PCI device
		into memory space as we are short of
		mappable memory */
		pci_slot_ignore \|= (1 << myslot);
		ret = 1;
		}

		out:
		return ret;
		}


		struct pci_bus pci_versatile_scan_bus(int nr, struct pci_sys_data sys)
		{
		return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys);
		}

		/*
		* V3_LB_BASE? - local bus address
		* V3_LB_MAP? - pci bus address
		*/
		void __init pci_versatile_preinit(void)
		{
		}

		void __init pci_versatile_postinit(void)
		{
		}


		/*
		* map the specified device/slot/pin to an IRQ. Different backplanes may need to modify this.
		*/
		static int __init versatile_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
		{
		int irq;
		int devslot = PCI_SLOT(dev->devfn);

		/* slot, pin, irq
		24 1 27
		25 1 28 untested
		26 1 29
		27 1 30 untested
		*/

		irq = 27 + ((slot + pin + 2) % 3); /* Fudged */

		printk("map irq: slot %d, pin %d, devslot %d, irq: %d\n",slot,pin,devslot,irq);

		return irq;
		}

		static struct hw_pci versatile_pci __initdata = {
		.swizzle = NULL,
		.map_irq = versatile_map_irq,
		.nr_controllers = 1,
		.setup = pci_versatile_setup,
		.scan = pci_versatile_scan_bus,
		.preinit = pci_versatile_preinit,
		.postinit = pci_versatile_postinit,
		};

		static int __init versatile_pci_init(void)
		{
		pci_common_init(&versatile_pci);
		return 0;
		}

		subsys_initcall(versatile_pci_init);

include/asm-arm/arch-versatile/hardware.h

+17 −10

Original line number	Diff line number	Diff line
		@@ -25,19 +25,26 @@
		#include <asm/sizes.h>
		#include <asm/arch/platform.h>

		// FIXME = PCI settings need to be fixed!!!!!

		/*
		* Similar to above, but for PCI addresses (memory, IO, Config and the
		* V3 chip itself). WARNING: this has to mirror definitions in platform.h
		* PCI space virtual addresses
		*/
		#define PCI_MEMORY_VADDR 0xe8000000
		#define PCI_CONFIG_VADDR 0xec000000
		#define PCI_V3_VADDR 0xed000000
		#define PCI_IO_VADDR 0xee000000
		#define VERSATILE_PCI_VIRT_BASE 0xe8000000
		#define VERSATILE_PCI_CFG_VIRT_BASE 0xe9000000

		#if 0
		#define VERSATILE_PCI_VIRT_MEM_BASE0 0xf4000000
		#define VERSATILE_PCI_VIRT_MEM_BASE1 0xf5000000
		#define VERSATILE_PCI_VIRT_MEM_BASE2 0xf6000000

		#define PCIO_BASE VERSATILE_PCI_VIRT_MEM_BASE0
		#define PCIMEM_BASE VERSATILE_PCI_VIRT_MEM_BASE1
		#endif

		/* CIK guesswork */
		#define PCIBIOS_MIN_IO 0x44000000
		#define PCIBIOS_MIN_MEM 0x50000000

		#define PCIO_BASE PCI_IO_VADDR
		#define PCIMEM_BASE PCI_MEMORY_VADDR
		#define pcibios_assign_all_busses() 1

		/* macro to get at IO space when running virtually */
		#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)