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Commit c0963f85 authored by Matt Wagantall's avatar Matt Wagantall
Browse files

coresight: remove provisions for Krait-CPU targets 



Krait CPU devices are not supported in the current msm-3.18 kernel.
Drop the now-unnecessary code.

Change-Id: I527fcac6840cf977fdc8770f25a7e75279771cf7
Signed-off-by: default avatarMatt Wagantall <mattw@codeaurora.org>
parent 0a56ad39

drivers/coresight/coresight-etm.c

+16 −78
Original line number Diff line number Diff line 
/* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.

/* Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -46,17 +46,11 @@ 


#define etm_writel(drvdata, val, off)					\

({									\

	if (cpu_is_krait_v3())						\

		etm_writel_cp14(val, off);				\

	else								\

	etm_writel_mm(drvdata, val, off);				\

})

#define etm_readl(drvdata, off)						\

({									\

	uint32_t val;							\

	if (cpu_is_krait_v3())						\

		val = etm_readl_cp14(off);				\

	else								\

	val = etm_readl_mm(drvdata, off);				\

	val;								\

})
@@ -305,16 +299,6 @@ static void etm_os_unlock(void *info) 
{

	struct etm_drvdata *drvdata = (struct etm_drvdata *) info;



	/*

	 * Memory mapped writes to clear os lock are not supported on Krait v1,

	 * v2 and OS lock must be unlocked before any memory mapped access,

	 * otherwise memory mapped reads/writes will be invalid.

	 */

	if (cpu_is_krait()) {

		etm_writel_cp14(0x0, ETMOSLAR);

		/* ensure os lock is unlocked before we return */

		isb();

	} else {

	ETM_UNLOCK(drvdata);

	if (etm_os_lock_present(drvdata)) {

		etm_writel(drvdata, 0x0, ETMOSLAR);
@@ -323,7 +307,6 @@ static void etm_os_unlock(void *info) 
	}

	ETM_LOCK(drvdata);

}

}



/*

 * ETM clock is derived from the processor clock and gets enabled on a
@@ -370,18 +353,9 @@ static void etm_set_pwrup(struct etm_drvdata *drvdata) 
	uint32_t cpmr;

	uint32_t etmpdcr;



	 /* For Krait, use cp15 CPMR_ETMCLKEN instead of ETMPDCR since ETMPDCR

	  * is not supported for this purpose on Krait v4.

	  */

	if (cpu_is_krait()) {

		asm volatile("mrc p15, 7, %0, c15, c0, 5" : "=r" (cpmr));

		cpmr  |= CPMR_ETMCLKEN;

		asm volatile("mcr p15, 7, %0, c15, c0, 5" : : "r" (cpmr));

	} else {

	etmpdcr = etm_readl_mm(drvdata, ETMPDCR);

	etmpdcr |= BIT(3);

	etm_writel_mm(drvdata, etmpdcr, ETMPDCR);

	}

	/* ensure pwrup completes before subsequent cp14 accesses */

	mb();

	isb();
@@ -395,19 +369,10 @@ static void etm_clr_pwrup(struct etm_drvdata *drvdata) 
	/* ensure pending cp14 accesses complete before clearing pwrup */

	mb();

	isb();

	 /* For Krait, use cp15 CPMR_ETMCLKEN instead of ETMPDCR since ETMPDCR

	  * is not supported for this purpose on Krait v4.

	  */

	if (cpu_is_krait()) {

		asm volatile("mrc p15, 7, %0, c15, c0, 5" : "=r" (cpmr));

		cpmr  &= ~CPMR_ETMCLKEN;

		asm volatile("mcr p15, 7, %0, c15, c0, 5" : : "r" (cpmr));

	} else {

	etmpdcr = etm_readl_mm(drvdata, ETMPDCR);

	etmpdcr &= ~BIT(3);

	etm_writel_mm(drvdata, etmpdcr, ETMPDCR);

}

}



static void etm_set_prog(struct etm_drvdata *drvdata)

{
@@ -494,10 +459,6 @@ static void etm_reset_data(struct etm_drvdata *drvdata) 
	drvdata->ctrl = 0x0;

	if (etm_version_gte(drvdata->arch, ETM_ARCH_V1_0))

		drvdata->ctrl |= BIT(11);

	if (cpu_is_krait_v1()) {

		drvdata->mode |= ETM_MODE_CYCACC;

		drvdata->ctrl |= BIT(12);

	}

	drvdata->trigger_event = 0x406F;

	drvdata->startstop_ctrl = 0x0;

	if (etm_version_gte(drvdata->arch, ETM_ARCH_V1_2))
@@ -541,10 +502,6 @@ static void etm_reset_data(struct etm_drvdata *drvdata) 
	for (i = 0; i < drvdata->nr_ctxid_cmp; i++)

		drvdata->ctxid_val[i] = 0x0;

	drvdata->ctxid_mask = 0x0;

	/* Bits[7:0] of ETMSYNCFR are reserved on Krait pass3 onwards */

	if (cpu_is_krait() && !cpu_is_krait_v1() && !cpu_is_krait_v2())

		drvdata->sync_freq = 0x100;

	else

	drvdata->sync_freq = 0x80;

	drvdata->timestamp_event = 0x406F;
@@ -2062,28 +2019,9 @@ static void etm_init_default_data(struct etm_drvdata *drvdata) 
	drvdata->seq_31_event = 0x406F;

	drvdata->seq_32_event = 0x406F;

	drvdata->seq_13_event = 0x406F;

	/* Bits[7:0] of ETMSYNCFR are reserved on Krait pass3 onwards */

	if (cpu_is_krait() && !cpu_is_krait_v1() && !cpu_is_krait_v2())

		drvdata->sync_freq = 0x100;

	else

	drvdata->sync_freq = 0x80;

	drvdata->timestamp_event = 0x406F;



	/* Overrides for Krait pass1 */

	if (cpu_is_krait_v1()) {

		/* Krait pass1 doesn't support include filtering and non-cycle

		 * accurate tracing

		 */

		drvdata->mode = (ETM_MODE_EXCLUDE | ETM_MODE_CYCACC);

		drvdata->ctrl = 0x1000;

		drvdata->enable_ctrl1 = 0x1000000;

		for (i = 0; i < drvdata->nr_addr_cmp; i++) {

			drvdata->addr_val[i] = 0x0;

			drvdata->addr_acctype[i] = 0x0;

			drvdata->addr_type[i] = ETM_ADDR_TYPE_NONE;

		}

	}



	if (etm_version_gte(drvdata->arch, ETM_ARCH_V1_0))

		drvdata->ctrl |= BIT(11);

	if (etm_version_gte(drvdata->arch, ETM_ARCH_V1_2))