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Commit c0481916 authored by Subbaraman Narayanamurthy's avatar Subbaraman Narayanamurthy
Browse files

power: qpnp-fg: remove configuring SOC_MAX/SOC_MIN interrupt thresholds 



Currently, SOC_MAX and SOC_MIN interrupt thresholds are allowed
to be configured via device tree or by default settings. However,
FG driver is not handling any interrupts associated with it.
Remove the code associated with it.

Change-Id: I9dcfcf29121f2723c069bfab66c05fbec50d3669
Signed-off-by: default avatarSubbaraman Narayanamurthy <subbaram@codeaurora.org>
parent 61a16a5e

Documentation/devicetree/bindings/power/qpnp-fg.txt

+0 −4
Original line number Diff line number Diff line
@@ -102,10 +102,6 @@ Parent node optional properties: 
					above 3-4, some period workarounds may

					not function well, so it's best to

					leave this at 1 or 2%.

- qcom,fg-soc-max:			The percent SoC threshold at which the

					HIGH_SOC interrupt will be asserted.

- qcom,fg-soc-min:			The percent SoC threshold at which the

					LOW_SOC interrupt will be asserted.

- qcom,fg-vbatt-low-threshold:		Voltage (in mV) which upon set will be

					used for configuring the low battery

					voltage threshold. Interrupt will be

drivers/power/qpnp-fg.c

+0 −22
Original line number Diff line number Diff line
@@ -198,8 +198,6 @@ enum fg_mem_setting_index { 
	FG_MEM_CUTOFF_VOLTAGE,

	FG_MEM_VBAT_EST_DIFF,

	FG_MEM_DELTA_SOC,

	FG_MEM_SOC_MAX,

	FG_MEM_SOC_MIN,

	FG_MEM_BATT_LOW,

	FG_MEM_THERM_DELAY,

	FG_MEM_SETTING_MAX,
@@ -245,8 +243,6 @@ static struct fg_mem_setting settings[FG_MEM_SETTING_MAX] = { 
	SETTING(CUTOFF_VOLTAGE,	 0x40C,   0,      3200),

	SETTING(VBAT_EST_DIFF,	 0x000,   0,      30),

	SETTING(DELTA_SOC,	 0x450,   3,      1),

	SETTING(SOC_MAX,	 0x458,   1,      85),

	SETTING(SOC_MIN,	 0x458,   2,      15),

	SETTING(BATT_LOW,	 0x458,   0,      4200),

	SETTING(THERM_DELAY,	 0x4AC,   3,      0),

};
@@ -5043,8 +5039,6 @@ static int fg_of_init(struct fg_chip *chip) 
	OF_READ_SETTING(FG_MEM_IRQ_VOLT_EMPTY, "irq-volt-empty-mv", rc, 1);

	OF_READ_SETTING(FG_MEM_VBAT_EST_DIFF, "vbat-estimate-diff-mv", rc, 1);

	OF_READ_SETTING(FG_MEM_DELTA_SOC, "fg-delta-soc", rc, 1);

	OF_READ_SETTING(FG_MEM_SOC_MAX, "fg-soc-max", rc, 1);

	OF_READ_SETTING(FG_MEM_SOC_MIN, "fg-soc-min", rc, 1);

	OF_READ_SETTING(FG_MEM_BATT_LOW, "fg-vbatt-low-threshold", rc, 1);

	OF_READ_SETTING(FG_MEM_THERM_DELAY, "fg-therm-delay-us", rc, 1);

	OF_READ_PROPERTY(chip->learning_data.max_increment,
@@ -5842,22 +5836,6 @@ static int fg_common_hw_init(struct fg_chip *chip) 
		return rc;

	}



	rc = fg_mem_masked_write(chip, settings[FG_MEM_SOC_MAX].address, 0xFF,

			soc_to_setpoint(settings[FG_MEM_SOC_MAX].value),

			settings[FG_MEM_SOC_MAX].offset);

	if (rc) {

		pr_err("failed to write soc_max rc=%d\n", rc);

		return rc;

	}



	rc = fg_mem_masked_write(chip, settings[FG_MEM_SOC_MIN].address, 0xFF,

			soc_to_setpoint(settings[FG_MEM_SOC_MIN].value),

			settings[FG_MEM_SOC_MIN].offset);

	if (rc) {

		pr_err("failed to write soc_min rc=%d\n", rc);

		return rc;

	}



	rc = fg_mem_masked_write(chip, settings[FG_MEM_BATT_LOW].address, 0xFF,

			batt_to_setpoint_8b(settings[FG_MEM_BATT_LOW].value),

			settings[FG_MEM_BATT_LOW].offset);