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Commit bf955823 authored by Amir Levy's avatar Amir Levy
Browse files

msm: ipa3: Added uC Event Ring memory region to IPA SRAM 



Since there is no dedicated descriptor RAM for uC in SDX20 and
SDM845, the event ring is added to IPA SRAM. The transfer ring is
placed in uC DRAM, since IPA only needs read access to it. However
the event ring cannot be placed in uC DRAM, since IPA needs to write
to it and this is forbidden per security policy. uC event ring get 1K
space from the bottom of the IPA SRAM allocation on account of the
modem memory region.

Change-Id: I596528b9232824addb4722272edd478c45ba1f0b
Acked-by: default avatarDmitry Kogan <dmitryk@qti.qualcomm.com>
Signed-off-by: default avatarAmir Levy <alevy@codeaurora.org>
parent 7e1165aa

drivers/platform/msm/ipa/ipa_v3/ipa.c

+22 −7
Original line number Diff line number Diff line
@@ -2380,12 +2380,7 @@ static inline void ipa3_sram_set_canary(u32 *sram_mmio, int offset) 
	sram_mmio[(offset - 4) / 4] = IPA_MEM_CANARY_VAL;

}



/**

 * _ipa_init_sram_v3_0() - Initialize IPA local SRAM.

 *

 * Return codes: 0 for success, negative value for failure

 */

int _ipa_init_sram_v3_0(void)

static int _ipa_init_sram_v3(int last_canary_offset)

{

	u32 *ipa_sram_mmio;

	unsigned long phys_addr;
@@ -2428,13 +2423,33 @@ int _ipa_init_sram_v3_0(void) 
		IPA_MEM_PART(modem_hdr_proc_ctx_ofst));

	ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(modem_ofst) - 4);

	ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(modem_ofst));

	ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(end_ofst));

	ipa3_sram_set_canary(ipa_sram_mmio, last_canary_offset);



	iounmap(ipa_sram_mmio);



	return 0;

}



/**

 * _ipa_init_sram_v3_0() - Initialize IPA 3.0 local SRAM.

 *

 * Return codes: 0 for success, negative value for failure

 */

int _ipa_init_sram_v3_0(void)

{

	return _ipa_init_sram_v3(IPA_MEM_PART(end_ofst));

}



/**

* _ipa_init_sram_v3_5() - Initialize IPA 3.5 local SRAM.

*

* Return codes: 0 for success, negative value for failure

*/

int _ipa_init_sram_v3_5(void)

{

	return _ipa_init_sram_v3(IPA_MEM_PART(uc_event_ring_ofst));

}



/**

 * _ipa_init_hdr_v3_0() - Initialize IPA header block.

 *

drivers/platform/msm/ipa/ipa_v3/ipa_i.h

+4 −0
Original line number Diff line number Diff line
@@ -1397,6 +1397,8 @@ struct ipa3_mem_partition { 
	u16 modem_comp_decomp_size;

	u16 modem_ofst;

	u16 modem_size;

	u16 uc_event_ring_ofst;

	u16 uc_event_ring_size;

	u16 apps_v4_flt_hash_ofst;

	u16 apps_v4_flt_hash_size;

	u16 apps_v4_flt_nhash_ofst;
@@ -1894,6 +1896,8 @@ int ipa3_teth_bridge_driver_init(void); 
void ipa3_lan_rx_cb(void *priv, enum ipa_dp_evt_type evt, unsigned long data);



int _ipa_init_sram_v3_0(void);

int _ipa_init_sram_v3_5(void);



int _ipa_init_hdr_v3_0(void);

int _ipa_init_rt4_v3(void);

int _ipa_init_rt6_v3(void);

drivers/platform/msm/ipa/ipa_v3/ipa_ram_mmap.h

+269 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.

/* Copyright (c) 2012-2015, 2017 The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -42,6 +42,8 @@ 
/*

 * IPA v3.0 SRAM memory layout:

 * +-------------------------+

 * |    UC MEM               |

 * +-------------------------+

 * |    UC INFO              |

 * +-------------------------+

 * |    CANARY               |
@@ -108,6 +110,8 @@ 
 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |  MODEM MEM              |

 * +-------------------------+

 * |    CANARY               |
@@ -304,4 +308,268 @@ 
#define IPA_MEM_v3_0_RAM_APPS_V6_RT_NHASH_SIZE 0

#define IPA_MEM_v3_0_RAM_HDR_SIZE_DDR 2048



/*

 * IPA v3.5 SRAM memory layout:

 * +-------------------------+

 * |    UC MEM               |

 * +-------------------------+

 * |    UC INFO              |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V4 FLT HDR HASHABLE     |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V4 FLT HDR NON-HASHABLE |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V6 FLT HDR HASHABLE     |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V6 FLT HDR NON-HASHABLE |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V4 RT HDR HASHABLE      |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V4 RT HDR NON-HASHABLE  |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V6 RT HDR HASHABLE      |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V6 RT HDR NON-HASHABLE  |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |  MODEM HDR              |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | MODEM PROC CTX          |

 * +-------------------------+

 * | APPS PROC CTX           |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |  MODEM MEM              |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |  UC EVENT RING          |

 * +-------------------------+

 */



/*

 * NOTE: Change in one off IPA v3.5 RAM offsets requires change in all

 *       subsequent offsets

 */

#define IPA_MEM_v3_5_RAM_UC_INFO_OFST IPA_MEM_v3_0_RAM_UC_INFO_OFST

#define IPA_MEM_v3_5_RAM_UC_INFO_SIZE IPA_MEM_v3_0_RAM_UC_INFO_SIZE



/* uC info 4B aligned */

#if (IPA_MEM_v3_5_RAM_UC_INFO_OFST & 3)

#error uC info is not 4B aligned

#endif



#define IPA_MEM_v3_5_RAM_OFST_START IPA_MEM_v3_0_RAM_OFST_START



#define IPA_MEM_v3_5_RAM_V4_FLT_HASH_OFST IPA_MEM_v3_0_RAM_V4_FLT_HASH_OFST

#define IPA_MEM_v3_5_RAM_V4_FLT_HASH_SIZE IPA_MEM_v3_0_RAM_V4_FLT_HASH_SIZE



/* V4 filtering hashable header table is 8B aligned */

#if (IPA_MEM_v3_5_RAM_V4_FLT_HASH_OFST & 7)

#error V4 filtering hashable header table is not 8B aligned

#endif



#define IPA_MEM_v3_5_RAM_V4_FLT_NHASH_OFST IPA_MEM_v3_0_RAM_V4_FLT_NHASH_OFST

#define IPA_MEM_v3_5_RAM_V4_FLT_NHASH_SIZE IPA_MEM_v3_0_RAM_V4_FLT_NHASH_SIZE



/* V4 filtering non-hashable header table is 8B aligned */

#if (IPA_MEM_v3_5_RAM_V4_FLT_NHASH_OFST & 7)

#error V4 filtering non-hashable header table is not 8B aligned

#endif



#define IPA_MEM_v3_5_RAM_V6_FLT_HASH_OFST IPA_MEM_v3_0_RAM_V6_FLT_HASH_OFST

#define IPA_MEM_v3_5_RAM_V6_FLT_HASH_SIZE IPA_MEM_v3_0_RAM_V6_FLT_HASH_SIZE



/* V6 filtering hashable header table is 8B aligned */

#if (IPA_MEM_v3_5_RAM_V6_FLT_HASH_OFST & 7)

#error V6 filtering hashable header table is not 8B aligned

#endif



#define IPA_MEM_v3_5_RAM_V6_FLT_NHASH_OFST IPA_MEM_v3_0_RAM_V6_FLT_NHASH_OFST

#define IPA_MEM_v3_5_RAM_V6_FLT_NHASH_SIZE IPA_MEM_v3_0_RAM_V6_FLT_NHASH_SIZE



/* V6 filtering non-hashable header table is 8B aligned */

#if (IPA_MEM_v3_5_RAM_V6_FLT_NHASH_OFST & 7)

#error V6 filtering header table is not 8B aligned

#endif



#define IPA_MEM_v3_5_RAM_V4_RT_NUM_INDEX IPA_MEM_v3_0_RAM_V4_RT_NUM_INDEX

#define IPA_MEM_v3_5_V4_MODEM_RT_INDEX_LO IPA_MEM_v3_0_V4_MODEM_RT_INDEX_LO

#define IPA_MEM_v3_5_V4_MODEM_RT_INDEX_HI IPA_MEM_v3_0_V4_MODEM_RT_INDEX_HI

#define IPA_MEM_v3_5_V4_APPS_RT_INDEX_LO IPA_MEM_v3_0_V4_APPS_RT_INDEX_LO

#define IPA_MEM_v3_5_V4_APPS_RT_INDEX_HI IPA_MEM_v3_0_V4_APPS_RT_INDEX_HI



#define IPA_MEM_v3_5_RAM_V4_RT_HASH_OFST IPA_MEM_v3_0_RAM_V4_RT_HASH_OFST

#define IPA_MEM_v3_5_RAM_V4_RT_HASH_SIZE IPA_MEM_v3_0_RAM_V4_RT_HASH_SIZE



/* V4 routing hashable header table is 8B aligned */

#if (IPA_MEM_v3_5_RAM_V4_RT_HASH_OFST & 7)

#error V4 routing hashable header table is not 8B aligned

#endif



#define IPA_MEM_v3_5_RAM_V4_RT_NHASH_OFST IPA_MEM_v3_0_RAM_V4_RT_NHASH_OFST

#define IPA_MEM_v3_5_RAM_V4_RT_NHASH_SIZE IPA_MEM_v3_0_RAM_V4_RT_NHASH_SIZE



/* V4 routing non-hashable header table is 8B aligned */

#if (IPA_MEM_v3_5_RAM_V4_RT_NHASH_OFST & 7)

#error V4 routing non-hashable header table is not 8B aligned

#endif



#define IPA_MEM_v3_5_RAM_V6_RT_NUM_INDEX IPA_MEM_v3_0_RAM_V6_RT_NUM_INDEX

#define IPA_MEM_v3_5_V6_MODEM_RT_INDEX_LO IPA_MEM_v3_0_V6_MODEM_RT_INDEX_LO

#define IPA_MEM_v3_5_V6_MODEM_RT_INDEX_HI IPA_MEM_v3_0_V6_MODEM_RT_INDEX_HI

#define IPA_MEM_v3_5_V6_APPS_RT_INDEX_LO IPA_MEM_v3_0_V6_APPS_RT_INDEX_LO

#define IPA_MEM_v3_5_V6_APPS_RT_INDEX_HI IPA_MEM_v3_0_V6_APPS_RT_INDEX_HI



#define IPA_MEM_v3_5_RAM_V6_RT_HASH_OFST IPA_MEM_v3_0_RAM_V6_RT_HASH_OFST

#define IPA_MEM_v3_5_RAM_V6_RT_HASH_SIZE IPA_MEM_v3_0_RAM_V6_RT_HASH_SIZE



/* V6 routing hashable header table is 8B aligned */

#if (IPA_MEM_v3_5_RAM_V6_RT_HASH_OFST & 7)

#error V6 routing hashable header table is not 8B aligned

#endif



#define IPA_MEM_v3_5_RAM_V6_RT_NHASH_OFST IPA_MEM_v3_0_RAM_V6_RT_NHASH_OFST

#define IPA_MEM_v3_5_RAM_V6_RT_NHASH_SIZE IPA_MEM_v3_0_RAM_V6_RT_NHASH_SIZE



/* V6 routing non-hashable header table is 8B aligned */

#if (IPA_MEM_v3_5_RAM_V6_RT_NHASH_OFST & 7)

#error V6 routing non-hashable header table is not 8B aligned

#endif



#define IPA_MEM_v3_5_RAM_MODEM_HDR_OFST IPA_MEM_v3_0_RAM_MODEM_HDR_OFST

#define IPA_MEM_v3_5_RAM_MODEM_HDR_SIZE IPA_MEM_v3_0_RAM_MODEM_HDR_SIZE



/* header table is 8B aligned */

#if (IPA_MEM_v3_5_RAM_MODEM_HDR_OFST & 7)

#error header table is not 8B aligned

#endif



#define IPA_MEM_v3_5_RAM_APPS_HDR_OFST IPA_MEM_v3_0_RAM_APPS_HDR_OFST

#define IPA_MEM_v3_5_RAM_APPS_HDR_SIZE IPA_MEM_v3_0_RAM_APPS_HDR_SIZE



/* header table is 8B aligned */

#if (IPA_MEM_v3_5_RAM_APPS_HDR_OFST & 7)

#error header table is not 8B aligned

#endif



#define IPA_MEM_v3_5_RAM_MODEM_HDR_PROC_CTX_OFST \

		IPA_MEM_v3_0_RAM_MODEM_HDR_PROC_CTX_OFST

#define IPA_MEM_v3_5_RAM_MODEM_HDR_PROC_CTX_SIZE \

		IPA_MEM_v3_0_RAM_MODEM_HDR_PROC_CTX_SIZE



/* header processing context table is 8B aligned */

#if (IPA_MEM_v3_5_RAM_MODEM_HDR_PROC_CTX_OFST & 7)

#error header processing context table is not 8B aligned

#endif



#define IPA_MEM_v3_5_RAM_APPS_HDR_PROC_CTX_OFST \

		IPA_MEM_v3_0_RAM_APPS_HDR_PROC_CTX_OFST

#define IPA_MEM_v3_5_RAM_APPS_HDR_PROC_CTX_SIZE \

		IPA_MEM_v3_0_RAM_APPS_HDR_PROC_CTX_SIZE



/* header processing context table is 8B aligned */

#if (IPA_MEM_v3_5_RAM_APPS_HDR_PROC_CTX_OFST & 7)

#error header processing context table is not 8B aligned

#endif



#define IPA_MEM_v3_5_RAM_MODEM_OFST IPA_MEM_v3_0_RAM_MODEM_OFST

#define IPA_MEM_v3_5_RAM_MODEM_SIZE 4132



/* modem memory is 8B aligned */

#if (IPA_MEM_v3_5_RAM_MODEM_OFST & 7)

#error modem memory is not 8B aligned

#endif



#define IPA_MEM_v3_5_UC_EVENT_RING_OFST (IPA_MEM_v3_5_RAM_MODEM_OFST + \

		IPA_MEM_v3_5_RAM_MODEM_SIZE + IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_5_UC_EVENT_RING_SIZE 1024



/* uC Event Ring memory is 1024B aligned */

#if (IPA_MEM_v3_5_UC_EVENT_RING_OFST & 1023)

#error uC Event Ring memory is not 1024B aligned

#endif



#define IPA_MEM_v3_5_RAM_APPS_V4_FLT_HASH_OFST \

		(IPA_MEM_v3_5_UC_EVENT_RING_OFST + \

		IPA_MEM_v3_5_UC_EVENT_RING_SIZE)

#define IPA_MEM_v3_5_RAM_APPS_V4_FLT_HASH_SIZE \

		IPA_MEM_v3_0_RAM_APPS_V4_FLT_HASH_SIZE



#define IPA_MEM_v3_5_RAM_APPS_V4_FLT_NHASH_OFST \

		(IPA_MEM_v3_5_RAM_APPS_V4_FLT_HASH_OFST + \

		IPA_MEM_v3_5_RAM_APPS_V4_FLT_HASH_SIZE)

#define IPA_MEM_v3_5_RAM_APPS_V4_FLT_NHASH_SIZE \

		IPA_MEM_v3_0_RAM_APPS_V4_FLT_NHASH_SIZE



#define IPA_MEM_v3_5_RAM_APPS_V6_FLT_HASH_OFST \

		(IPA_MEM_v3_5_RAM_APPS_V4_FLT_NHASH_OFST + \

		IPA_MEM_v3_5_RAM_APPS_V4_FLT_NHASH_SIZE)

#define IPA_MEM_v3_5_RAM_APPS_V6_FLT_HASH_SIZE \

		IPA_MEM_v3_0_RAM_APPS_V6_FLT_HASH_SIZE



#define IPA_MEM_v3_5_RAM_APPS_V6_FLT_NHASH_OFST \

		(IPA_MEM_v3_5_RAM_APPS_V6_FLT_HASH_OFST + \

		IPA_MEM_v3_5_RAM_APPS_V6_FLT_HASH_SIZE)

#define IPA_MEM_v3_5_RAM_APPS_V6_FLT_NHASH_SIZE \

		IPA_MEM_v3_0_RAM_APPS_V6_FLT_NHASH_SIZE



#define IPA_MEM_v3_5_RAM_END_OFST (IPA_MEM_v3_5_RAM_APPS_V6_FLT_NHASH_OFST + \

		IPA_MEM_v3_5_RAM_APPS_V6_FLT_NHASH_SIZE)

#define IPA_MEM_v3_5_RAM_APPS_V4_RT_HASH_OFST IPA_MEM_v3_5_RAM_END_OFST

#define IPA_MEM_v3_5_RAM_APPS_V4_RT_HASH_SIZE \

		IPA_MEM_v3_0_RAM_APPS_V4_RT_HASH_SIZE

#define IPA_MEM_v3_5_RAM_APPS_V4_RT_NHASH_OFST IPA_MEM_v3_5_RAM_END_OFST

#define IPA_MEM_v3_5_RAM_APPS_V4_RT_NHASH_SIZE \

		IPA_MEM_v3_0_RAM_APPS_V4_RT_NHASH_SIZE

#define IPA_MEM_v3_5_RAM_APPS_V6_RT_HASH_OFST IPA_MEM_v3_5_RAM_END_OFST

#define IPA_MEM_v3_5_RAM_APPS_V6_RT_HASH_SIZE \

		IPA_MEM_v3_0_RAM_APPS_V6_RT_HASH_SIZE

#define IPA_MEM_v3_5_RAM_APPS_V6_RT_NHASH_OFST IPA_MEM_v3_5_RAM_END_OFST

#define IPA_MEM_v3_5_RAM_APPS_V6_RT_NHASH_SIZE \

		IPA_MEM_v3_0_RAM_APPS_V6_RT_NHASH_SIZE

#define IPA_MEM_v3_5_RAM_HDR_SIZE_DDR IPA_MEM_v3_0_RAM_HDR_SIZE_DDR



#endif /* _IPA_RAM_MMAP_H_ */

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

+223 −2
Original line number Diff line number Diff line
@@ -4722,6 +4722,222 @@ static void ipa_init_mem_partition_v3_0(void) 
		IPA_MEM_v3_0_RAM_APPS_V6_RT_NHASH_SIZE;

}



static void ipa_init_mem_partition_v3_5(void)

{

	IPADBG("Memory partition IPA 3.5\n");

	IPA_MEM_PART(nat_ofst) = IPA_RAM_NAT_OFST;

	IPA_MEM_PART(nat_size) = IPA_RAM_NAT_SIZE;

	IPADBG("NAT OFST 0x%x SIZE 0x%x\n", IPA_MEM_PART(nat_ofst),

		IPA_MEM_PART(nat_size));



	IPA_MEM_PART(uc_info_ofst) = IPA_MEM_v3_5_RAM_UC_INFO_OFST;

	IPA_MEM_PART(uc_info_size) = IPA_MEM_v3_5_RAM_UC_INFO_SIZE;

	IPADBG("UC INFO OFST 0x%x SIZE 0x%x\n", IPA_MEM_PART(uc_info_ofst),

		IPA_MEM_PART(uc_info_size));



	IPA_MEM_PART(ofst_start) = IPA_MEM_v3_5_RAM_OFST_START;

	IPADBG("RAM OFST 0x%x\n", IPA_MEM_PART(ofst_start));



	IPA_MEM_PART(v4_flt_hash_ofst) = IPA_MEM_v3_5_RAM_V4_FLT_HASH_OFST;

	IPA_MEM_PART(v4_flt_hash_size) = IPA_MEM_v3_5_RAM_V4_FLT_HASH_SIZE;

	IPA_MEM_PART(v4_flt_hash_size_ddr) = IPA_MEM_RAM_V4_FLT_HASH_SIZE_DDR;

	IPADBG("V4 FLT HASHABLE OFST 0x%x SIZE 0x%x DDR SIZE 0x%x\n",

		IPA_MEM_PART(v4_flt_hash_ofst),

		IPA_MEM_PART(v4_flt_hash_size),

		IPA_MEM_PART(v4_flt_hash_size_ddr));



	IPA_MEM_PART(v4_flt_nhash_ofst) = IPA_MEM_v3_5_RAM_V4_FLT_NHASH_OFST;

	IPA_MEM_PART(v4_flt_nhash_size) = IPA_MEM_v3_5_RAM_V4_FLT_NHASH_SIZE;

	IPA_MEM_PART(v4_flt_nhash_size_ddr) = IPA_MEM_RAM_V4_FLT_NHASH_SIZE_DDR;

	IPADBG("V4 FLT NON-HASHABLE OFST 0x%x SIZE 0x%x DDR SIZE 0x%x\n",

		IPA_MEM_PART(v4_flt_nhash_ofst),

		IPA_MEM_PART(v4_flt_nhash_size),

		IPA_MEM_PART(v4_flt_nhash_size_ddr));



	IPA_MEM_PART(v6_flt_hash_ofst) = IPA_MEM_v3_5_RAM_V6_FLT_HASH_OFST;

	IPA_MEM_PART(v6_flt_hash_size) = IPA_MEM_v3_5_RAM_V6_FLT_HASH_SIZE;

	IPA_MEM_PART(v6_flt_hash_size_ddr) = IPA_MEM_RAM_V6_FLT_HASH_SIZE_DDR;

	IPADBG("V6 FLT HASHABLE OFST 0x%x SIZE 0x%x DDR SIZE 0x%x\n",

		IPA_MEM_PART(v6_flt_hash_ofst), IPA_MEM_PART(v6_flt_hash_size),

		IPA_MEM_PART(v6_flt_hash_size_ddr));



	IPA_MEM_PART(v6_flt_nhash_ofst) = IPA_MEM_v3_5_RAM_V6_FLT_NHASH_OFST;

	IPA_MEM_PART(v6_flt_nhash_size) = IPA_MEM_v3_5_RAM_V6_FLT_NHASH_SIZE;

	IPA_MEM_PART(v6_flt_nhash_size_ddr) = IPA_MEM_RAM_V6_FLT_NHASH_SIZE_DDR;

	IPADBG("V6 FLT NON-HASHABLE OFST 0x%x SIZE 0x%x DDR SIZE 0x%x\n",

		IPA_MEM_PART(v6_flt_nhash_ofst),

		IPA_MEM_PART(v6_flt_nhash_size),

		IPA_MEM_PART(v6_flt_nhash_size_ddr));



	IPA_MEM_PART(v4_rt_num_index) = IPA_MEM_v3_5_RAM_V4_RT_NUM_INDEX;

	IPADBG("V4 RT NUM INDEX 0x%x\n", IPA_MEM_PART(v4_rt_num_index));



	IPA_MEM_PART(v4_modem_rt_index_lo) =

		IPA_MEM_v3_5_V4_MODEM_RT_INDEX_LO;

	IPA_MEM_PART(v4_modem_rt_index_hi) =

		IPA_MEM_v3_5_V4_MODEM_RT_INDEX_HI;

	IPADBG("V4 RT MODEM INDEXES 0x%x - 0x%x\n",

		IPA_MEM_PART(v4_modem_rt_index_lo),

		IPA_MEM_PART(v4_modem_rt_index_hi));



	IPA_MEM_PART(v4_apps_rt_index_lo) =

		IPA_MEM_v3_5_V4_APPS_RT_INDEX_LO;

	IPA_MEM_PART(v4_apps_rt_index_hi) =

		IPA_MEM_v3_5_V4_APPS_RT_INDEX_HI;

	IPADBG("V4 RT APPS INDEXES 0x%x - 0x%x\n",

		IPA_MEM_PART(v4_apps_rt_index_lo),

		IPA_MEM_PART(v4_apps_rt_index_hi));



	IPA_MEM_PART(v4_rt_hash_ofst) = IPA_MEM_v3_5_RAM_V4_RT_HASH_OFST;

	IPADBG("V4 RT HASHABLE OFST 0x%x\n", IPA_MEM_PART(v4_rt_hash_ofst));



	IPA_MEM_PART(v4_rt_hash_size) = IPA_MEM_v3_5_RAM_V4_RT_HASH_SIZE;

	IPA_MEM_PART(v4_rt_hash_size_ddr) = IPA_MEM_RAM_V4_RT_HASH_SIZE_DDR;

	IPADBG("V4 RT HASHABLE SIZE 0x%x DDR SIZE 0x%x\n",

		IPA_MEM_PART(v4_rt_hash_size),

		IPA_MEM_PART(v4_rt_hash_size_ddr));



	IPA_MEM_PART(v4_rt_nhash_ofst) = IPA_MEM_v3_5_RAM_V4_RT_NHASH_OFST;

	IPADBG("V4 RT NON-HASHABLE OFST 0x%x\n",

		IPA_MEM_PART(v4_rt_nhash_ofst));



	IPA_MEM_PART(v4_rt_nhash_size) = IPA_MEM_v3_5_RAM_V4_RT_NHASH_SIZE;

	IPA_MEM_PART(v4_rt_nhash_size_ddr) = IPA_MEM_RAM_V4_RT_NHASH_SIZE_DDR;

	IPADBG("V4 RT HASHABLE SIZE 0x%x DDR SIZE 0x%x\n",

		IPA_MEM_PART(v4_rt_nhash_size),

		IPA_MEM_PART(v4_rt_nhash_size_ddr));



	IPA_MEM_PART(v6_rt_num_index) = IPA_MEM_v3_5_RAM_V6_RT_NUM_INDEX;

	IPADBG("V6 RT NUM INDEX 0x%x\n", IPA_MEM_PART(v6_rt_num_index));



	IPA_MEM_PART(v6_modem_rt_index_lo) =

		IPA_MEM_v3_5_V6_MODEM_RT_INDEX_LO;

	IPA_MEM_PART(v6_modem_rt_index_hi) =

		IPA_MEM_v3_5_V6_MODEM_RT_INDEX_HI;

	IPADBG("V6 RT MODEM INDEXES 0x%x - 0x%x\n",

		IPA_MEM_PART(v6_modem_rt_index_lo),

		IPA_MEM_PART(v6_modem_rt_index_hi));



	IPA_MEM_PART(v6_apps_rt_index_lo) =

		IPA_MEM_v3_5_V6_APPS_RT_INDEX_LO;

	IPA_MEM_PART(v6_apps_rt_index_hi) =

		IPA_MEM_v3_5_V6_APPS_RT_INDEX_HI;

	IPADBG("V6 RT APPS INDEXES 0x%x - 0x%x\n",

		IPA_MEM_PART(v6_apps_rt_index_lo),

		IPA_MEM_PART(v6_apps_rt_index_hi));



	IPA_MEM_PART(v6_rt_hash_ofst) = IPA_MEM_v3_5_RAM_V6_RT_HASH_OFST;

	IPADBG("V6 RT HASHABLE OFST 0x%x\n", IPA_MEM_PART(v6_rt_hash_ofst));



	IPA_MEM_PART(v6_rt_hash_size) = IPA_MEM_v3_5_RAM_V6_RT_HASH_SIZE;

	IPA_MEM_PART(v6_rt_hash_size_ddr) = IPA_MEM_RAM_V6_RT_HASH_SIZE_DDR;

	IPADBG("V6 RT HASHABLE SIZE 0x%x DDR SIZE 0x%x\n",

		IPA_MEM_PART(v6_rt_hash_size),

		IPA_MEM_PART(v6_rt_hash_size_ddr));



	IPA_MEM_PART(v6_rt_nhash_ofst) = IPA_MEM_v3_5_RAM_V6_RT_NHASH_OFST;

	IPADBG("V6 RT NON-HASHABLE OFST 0x%x\n",

		IPA_MEM_PART(v6_rt_nhash_ofst));



	IPA_MEM_PART(v6_rt_nhash_size) = IPA_MEM_v3_5_RAM_V6_RT_NHASH_SIZE;

	IPA_MEM_PART(v6_rt_nhash_size_ddr) = IPA_MEM_RAM_V6_RT_NHASH_SIZE_DDR;

	IPADBG("V6 RT NON-HASHABLE SIZE 0x%x DDR SIZE 0x%x\n",

		IPA_MEM_PART(v6_rt_nhash_size),

		IPA_MEM_PART(v6_rt_nhash_size_ddr));



	IPA_MEM_PART(modem_hdr_ofst) = IPA_MEM_v3_5_RAM_MODEM_HDR_OFST;

	IPA_MEM_PART(modem_hdr_size) = IPA_MEM_v3_5_RAM_MODEM_HDR_SIZE;

	IPADBG("MODEM HDR OFST 0x%x SIZE 0x%x\n",

		IPA_MEM_PART(modem_hdr_ofst), IPA_MEM_PART(modem_hdr_size));



	IPA_MEM_PART(apps_hdr_ofst) = IPA_MEM_v3_5_RAM_APPS_HDR_OFST;

	IPA_MEM_PART(apps_hdr_size) = IPA_MEM_v3_5_RAM_APPS_HDR_SIZE;

	IPA_MEM_PART(apps_hdr_size_ddr) = IPA_MEM_v3_5_RAM_HDR_SIZE_DDR;

	IPADBG("APPS HDR OFST 0x%x SIZE 0x%x DDR SIZE 0x%x\n",

		IPA_MEM_PART(apps_hdr_ofst), IPA_MEM_PART(apps_hdr_size),

		IPA_MEM_PART(apps_hdr_size_ddr));



	IPA_MEM_PART(modem_hdr_proc_ctx_ofst) =

		IPA_MEM_v3_5_RAM_MODEM_HDR_PROC_CTX_OFST;

	IPA_MEM_PART(modem_hdr_proc_ctx_size) =

		IPA_MEM_v3_5_RAM_MODEM_HDR_PROC_CTX_SIZE;

	IPADBG("MODEM HDR PROC CTX OFST 0x%x SIZE 0x%x\n",

		IPA_MEM_PART(modem_hdr_proc_ctx_ofst),

		IPA_MEM_PART(modem_hdr_proc_ctx_size));



	IPA_MEM_PART(apps_hdr_proc_ctx_ofst) =

		IPA_MEM_v3_5_RAM_APPS_HDR_PROC_CTX_OFST;

	IPA_MEM_PART(apps_hdr_proc_ctx_size) =

		IPA_MEM_v3_5_RAM_APPS_HDR_PROC_CTX_SIZE;

	IPA_MEM_PART(apps_hdr_proc_ctx_size_ddr) =

		IPA_MEM_RAM_HDR_PROC_CTX_SIZE_DDR;

	IPADBG("APPS HDR PROC CTX OFST 0x%x SIZE 0x%x DDR SIZE 0x%x\n",

		IPA_MEM_PART(apps_hdr_proc_ctx_ofst),

		IPA_MEM_PART(apps_hdr_proc_ctx_size),

		IPA_MEM_PART(apps_hdr_proc_ctx_size_ddr));



	IPA_MEM_PART(modem_ofst) = IPA_MEM_v3_5_RAM_MODEM_OFST;

	IPA_MEM_PART(modem_size) = IPA_MEM_v3_5_RAM_MODEM_SIZE;

	IPADBG("MODEM OFST 0x%x SIZE 0x%x\n", IPA_MEM_PART(modem_ofst),

		IPA_MEM_PART(modem_size));



	IPA_MEM_PART(uc_event_ring_ofst) = IPA_MEM_v3_5_UC_EVENT_RING_OFST;

	IPA_MEM_PART(uc_event_ring_size) = IPA_MEM_v3_5_UC_EVENT_RING_SIZE;

	IPADBG("UC EVENT RING OFST 0x%x SIZE 0x%x\n",

		IPA_MEM_PART(uc_event_ring_ofst),

		IPA_MEM_PART(uc_event_ring_size));



	IPA_MEM_PART(apps_v4_flt_hash_ofst) =

		IPA_MEM_v3_5_RAM_APPS_V4_FLT_HASH_OFST;

	IPA_MEM_PART(apps_v4_flt_hash_size) =

		IPA_MEM_v3_5_RAM_APPS_V4_FLT_HASH_SIZE;

	IPADBG("V4 APPS HASHABLE FLT OFST 0x%x SIZE 0x%x\n",

		IPA_MEM_PART(apps_v4_flt_hash_ofst),

		IPA_MEM_PART(apps_v4_flt_hash_size));



	IPA_MEM_PART(apps_v4_flt_nhash_ofst) =

		IPA_MEM_v3_5_RAM_APPS_V4_FLT_NHASH_OFST;

	IPA_MEM_PART(apps_v4_flt_nhash_size) =

		IPA_MEM_v3_5_RAM_APPS_V4_FLT_NHASH_SIZE;

	IPADBG("V4 APPS NON-HASHABLE FLT OFST 0x%x SIZE 0x%x\n",

		IPA_MEM_PART(apps_v4_flt_nhash_ofst),

		IPA_MEM_PART(apps_v4_flt_nhash_size));



	IPA_MEM_PART(apps_v6_flt_hash_ofst) =

		IPA_MEM_v3_5_RAM_APPS_V6_FLT_HASH_OFST;

	IPA_MEM_PART(apps_v6_flt_hash_size) =

		IPA_MEM_v3_5_RAM_APPS_V6_FLT_HASH_SIZE;

	IPADBG("V6 APPS HASHABLE FLT OFST 0x%x SIZE 0x%x\n",

		IPA_MEM_PART(apps_v6_flt_hash_ofst),

		IPA_MEM_PART(apps_v6_flt_hash_size));



	IPA_MEM_PART(apps_v6_flt_nhash_ofst) =

		IPA_MEM_v3_5_RAM_APPS_V6_FLT_NHASH_OFST;

	IPA_MEM_PART(apps_v6_flt_nhash_size) =

		IPA_MEM_v3_5_RAM_APPS_V6_FLT_NHASH_SIZE;

	IPADBG("V6 APPS NON-HASHABLE FLT OFST 0x%x SIZE 0x%x\n",

		IPA_MEM_PART(apps_v6_flt_nhash_ofst),

		IPA_MEM_PART(apps_v6_flt_nhash_size));



	IPA_MEM_PART(end_ofst) = IPA_MEM_v3_5_RAM_END_OFST;

	IPA_MEM_PART(apps_v4_rt_hash_ofst) =

		IPA_MEM_v3_5_RAM_APPS_V4_RT_HASH_OFST;

	IPA_MEM_PART(apps_v4_rt_hash_size) =

		IPA_MEM_v3_5_RAM_APPS_V4_RT_HASH_SIZE;

	IPA_MEM_PART(apps_v4_rt_nhash_ofst) =

		IPA_MEM_v3_5_RAM_APPS_V4_RT_NHASH_OFST;

	IPA_MEM_PART(apps_v4_rt_nhash_size) =

		IPA_MEM_v3_5_RAM_APPS_V4_RT_NHASH_SIZE;

	IPA_MEM_PART(apps_v6_rt_hash_ofst) =

		IPA_MEM_v3_5_RAM_APPS_V6_RT_HASH_OFST;

	IPA_MEM_PART(apps_v6_rt_hash_size) =

		IPA_MEM_v3_5_RAM_APPS_V6_RT_HASH_SIZE;

	IPA_MEM_PART(apps_v6_rt_nhash_ofst) =

		IPA_MEM_v3_5_RAM_APPS_V6_RT_NHASH_OFST;

	IPA_MEM_PART(apps_v6_rt_nhash_size) =

		IPA_MEM_v3_5_RAM_APPS_V6_RT_NHASH_SIZE;

}



/**

 * ipa_ctrl_static_bind() - set the appropriate methods for

 *  IPA Driver based on the HW version
@@ -4735,7 +4951,13 @@ static void ipa_init_mem_partition_v3_0(void) 
int ipa3_controller_static_bind(struct ipa3_controller *ctrl,

		enum ipa_hw_type hw_type)

{

	if (hw_type >= IPA_HW_v3_5) {

		ipa_init_mem_partition_v3_5();

		ctrl->ipa_init_sram = _ipa_init_sram_v3_5;

	} else {

		ipa_init_mem_partition_v3_0();

		ctrl->ipa_init_sram = _ipa_init_sram_v3_0;

	}



	ctrl->ipa_init_rt4 = _ipa_init_rt4_v3;

	ctrl->ipa_init_rt6 = _ipa_init_rt6_v3;
@@ -4756,7 +4978,6 @@ int ipa3_controller_static_bind(struct ipa3_controller *ctrl, 
	ctrl->clock_scaling_bw_threshold_turbo =

		IPA_V3_0_BW_THRESHOLD_TURBO_MBPS;

	ctrl->ipa_reg_base_ofst = ipahal_get_reg_base();

	ctrl->ipa_init_sram = _ipa_init_sram_v3_0;

	ctrl->ipa_sram_read_settings = _ipa_sram_settings_read_v3_0;



	ctrl->ipa_init_hdr = _ipa_init_hdr_v3_0;