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Commit bf11ed65 authored by Yan He's avatar Yan He
Browse files

msm: ep_pcie: set up execution environment before link up 



Set up the execution environment before PCIe link training to
provide better adaptability to various hosts.

Change-Id: I72721d3b88a7e5b1a0a1f408da2228391559468e
Signed-off-by: default avatarYan He <yanhe@codeaurora.org>
parent c42ceee6

drivers/platform/msm/ep_pcie/ep_pcie_com.h

+3 −0
Original line number Original line Diff line number Diff line
@@ -95,6 +95,9 @@ 
#define PCIE20_PLR_IATU_LTAR           0x918

#define PCIE20_PLR_IATU_LTAR           0x918

#define PCIE20_PLR_IATU_UTAR           0x91c

#define PCIE20_PLR_IATU_UTAR           0x91c





#define PCIE20_MHICFG                  0x110

#define PCIE20_BHI_EXECENV             0x228



#define PCIE20_AUX_CLK_FREQ_REG        0xB40

#define PCIE20_AUX_CLK_FREQ_REG        0xB40





#define PERST_TIMEOUT_US_MIN	              1000

#define PERST_TIMEOUT_US_MIN	              1000

drivers/platform/msm/ep_pcie/ep_pcie_core.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -557,6 +557,9 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev) 
	/* Configure BARs */

	/* Configure BARs */

	ep_pcie_bar_init(dev);

	ep_pcie_bar_init(dev);





	ep_pcie_write_reg(dev->mmio, PCIE20_MHICFG, 0x02800880);

	ep_pcie_write_reg(dev->mmio, PCIE20_BHI_EXECENV, 0x2);



	/* Configure IRQ events */

	/* Configure IRQ events */

	if (dev->aggregated_irq) {

	if (dev->aggregated_irq) {

		ep_pcie_write_reg(dev->parf, PCIE20_PARF_INT_ALL_MASK, 0);

		ep_pcie_write_reg(dev->parf, PCIE20_PARF_INT_ALL_MASK, 0);