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Commit bee6c03c authored by Anirudh Ghayal's avatar Anirudh Ghayal Committed by Gerrit - the friendly Code Review server
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power: qpnp-fg-gen3: Configure sync-sleep threshold 



Add a DT property to configure the sync-sleep threshold.

Change-Id: I3fdccd37eb59e0c55f8b32a7358a767a067a3ab9
Signed-off-by: default avatarAnirudh Ghayal <aghayal@codeaurora.org>
parent 0ed50fb1

Documentation/devicetree/bindings/power/qpnp-fg-gen3.txt

+5 −0
Original line number Diff line number Diff line
@@ -412,6 +412,11 @@ First Level Node - FG Gen3 device 
	Definition: A boolean property which disables ESR pull-down.

		    This is to be used for debug purposes only.



- qcom,fg-sync-sleep-threshold-ma

	Usage:      optional

	Value type: <u32>

	Definition: The minimum battery current for FG to enter into sync-sleep.



==========================================================

Second Level Nodes - Peripherals managed by FG Gen3 driver

==========================================================

drivers/power/fg-core.h

+2 −0
Original line number Diff line number Diff line
@@ -177,6 +177,7 @@ enum fg_sram_param_id { 
	FG_SRAM_DELTA_MSOC_THR,

	FG_SRAM_DELTA_BSOC_THR,

	FG_SRAM_RECHARGE_SOC_THR,

	FG_SRAM_SYNC_SLEEP_THR,

	FG_SRAM_RECHARGE_VBATT_THR,

	FG_SRAM_KI_COEFF_MED_DISCHG,

	FG_SRAM_KI_COEFF_HI_DISCHG,
@@ -278,6 +279,7 @@ struct fg_dt_props { 
	int	slope_limit_temp;

	int	esr_pulse_thresh_ma;

	int	esr_meas_curr_ma;

	int	sync_sleep_threshold_ma;

	int	jeita_thresholds[NUM_JEITA_LEVELS];

	int	ki_coeff_soc[KI_COEFF_SOC_LEVELS];

	int	ki_coeff_med_dischg[KI_COEFF_SOC_LEVELS];

drivers/power/qpnp-fg-gen3.c

+31 −0
Original line number Diff line number Diff line
@@ -66,6 +66,8 @@ 
#define RECHARGE_SOC_THR_OFFSET		0

#define CHG_TERM_CURR_WORD		14

#define CHG_TERM_CURR_OFFSET		1

#define SYNC_SLEEP_THR_WORD		14

#define SYNC_SLEEP_THR_OFFSET		3

#define EMPTY_VOLT_WORD			15

#define EMPTY_VOLT_OFFSET		0

#define VBATT_LOW_WORD			15
@@ -135,6 +137,8 @@ 
#define DELTA_MSOC_THR_v2_OFFSET	0

#define RECHARGE_SOC_THR_v2_WORD	14

#define RECHARGE_SOC_THR_v2_OFFSET	1

#define SYNC_SLEEP_THR_v2_WORD		14

#define SYNC_SLEEP_THR_v2_OFFSET	2

#define CHG_TERM_CURR_v2_WORD		15

#define CHG_TERM_BASE_CURR_v2_OFFSET	0

#define CHG_TERM_CURR_v2_OFFSET		1
@@ -219,6 +223,8 @@ static struct fg_sram_param pmi8998_v1_sram_params[] = { 
		2048, 100, 0, fg_encode_default, NULL),

	PARAM(RECHARGE_SOC_THR, RECHARGE_SOC_THR_WORD, RECHARGE_SOC_THR_OFFSET,

		1, 256, 100, 0, fg_encode_default, NULL),

	PARAM(SYNC_SLEEP_THR, SYNC_SLEEP_THR_WORD, SYNC_SLEEP_THR_OFFSET,

		1, 100000, 390625, 0, fg_encode_default, NULL),

	PARAM(ESR_TIMER_DISCHG_MAX, ESR_TIMER_DISCHG_MAX_WORD,

		ESR_TIMER_DISCHG_MAX_OFFSET, 2, 1, 1, 0, fg_encode_default,

		NULL),
@@ -298,6 +304,8 @@ static struct fg_sram_param pmi8998_v2_sram_params[] = { 
	PARAM(RECHARGE_SOC_THR, RECHARGE_SOC_THR_v2_WORD,

		RECHARGE_SOC_THR_v2_OFFSET, 1, 256, 100, 0, fg_encode_default,

		NULL),

	PARAM(SYNC_SLEEP_THR, SYNC_SLEEP_THR_v2_WORD, SYNC_SLEEP_THR_v2_OFFSET,

		1, 100000, 390625, 0, fg_encode_default, NULL),

	PARAM(RECHARGE_VBATT_THR, RECHARGE_VBATT_THR_v2_WORD,

		RECHARGE_VBATT_THR_v2_OFFSET, 1, 1000, 15625, -2000,

		fg_encode_voltage, NULL),
@@ -3747,6 +3755,21 @@ static int fg_hw_init(struct fg_chip *chip) 
		}

	}



	if (chip->dt.sync_sleep_threshold_ma != -EINVAL) {

		fg_encode(chip->sp, FG_SRAM_SYNC_SLEEP_THR,

			chip->dt.sync_sleep_threshold_ma, buf);

		rc = fg_sram_write(chip,

				chip->sp[FG_SRAM_SYNC_SLEEP_THR].addr_word,

				chip->sp[FG_SRAM_SYNC_SLEEP_THR].addr_byte, buf,

				chip->sp[FG_SRAM_SYNC_SLEEP_THR].len,

				FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing sync_sleep_threshold=%d\n",

				rc);

			return rc;

		}

	}



	return 0;

}
@@ -4635,6 +4658,14 @@ static int fg_parse_dt(struct fg_chip *chip) 
			chip->dt.esr_meas_curr_ma = temp;

	}



	chip->dt.sync_sleep_threshold_ma = -EINVAL;

	rc = of_property_read_u32(node,

		"qcom,fg-sync-sleep-threshold-ma", &temp);

	if (!rc) {

		if (temp >= 0 && temp < 997)

			chip->dt.sync_sleep_threshold_ma = temp;

	}



	chip->dt.use_esr_sw = of_property_read_bool(node, "qcom,fg-use-sw-esr");



	chip->dt.disable_esr_pull_dn = of_property_read_bool(node,