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Commit bedfb7ad authored by Oleg Matcovschi's avatar Oleg Matcovschi Committed by Tony Lindgren
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ARM: OMAP: dma: Clear status registers on enable/disable irq 



Use omap_disable_channel_irq() function instead of directly accessing CICR
register in various functions.

The omap_disable_chanel_irq() function now clears pending interrupts
and disables interrupt on channel.

Functions omap2_enable_irq_lch()/omap2_disable_irq_lch() clear interrupt
status register.

Signed-off-by: default avatarOleg Matcovschi <oleg.matcovschi@ti.com>
Tested-by: default avatarJarkko Nikula <jarkko.nikula@bitmer.com>
[tony@atomide.com: updated comments to clarify CICR access]
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent f8f5701b

arch/arm/plat-omap/dma.c

+28 −31
Original line number Diff line number Diff line
@@ -573,22 +573,25 @@ EXPORT_SYMBOL(omap_set_dma_dest_burst_mode); 


static inline void omap_enable_channel_irq(int lch)

{

	u32 status;



	/* Clear CSR */

	if (cpu_class_is_omap1())

		status = p->dma_read(CSR, lch);

	else if (cpu_class_is_omap2())

		p->dma_read(CSR, lch);

	else

		p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);



	/* Enable some nice interrupts. */

	p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);

}



static void omap_disable_channel_irq(int lch)

static inline void omap_disable_channel_irq(int lch)

{

	if (cpu_class_is_omap2())

	/* disable channel interrupts */

	p->dma_write(0, CICR, lch);

	/* Clear CSR */

	if (cpu_class_is_omap1())

		p->dma_read(CSR, lch);

	else

		p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);

}



void omap_enable_dma_irq(int lch, u16 bits)
@@ -632,14 +635,14 @@ static inline void disable_lnk(int lch) 
	l = p->dma_read(CLNK_CTRL, lch);



	/* Disable interrupts */

	omap_disable_channel_irq(lch);



	if (cpu_class_is_omap1()) {

		p->dma_write(0, CICR, lch);

		/* Set the STOP_LNK bit */

		l |= 1 << 14;

	}



	if (cpu_class_is_omap2()) {

		omap_disable_channel_irq(lch);

		/* Clear the ENABLE_LNK bit */

		l &= ~(1 << 15);

	}
@@ -657,6 +660,9 @@ static inline void omap2_enable_irq_lch(int lch) 
		return;



	spin_lock_irqsave(&dma_chan_lock, flags);

	/* clear IRQ STATUS */

	p->dma_write(1 << lch, IRQSTATUS_L0, lch);

	/* Enable interrupt */

	val = p->dma_read(IRQENABLE_L0, lch);

	val |= 1 << lch;

	p->dma_write(val, IRQENABLE_L0, lch);
@@ -672,9 +678,12 @@ static inline void omap2_disable_irq_lch(int lch) 
		return;



	spin_lock_irqsave(&dma_chan_lock, flags);

	/* Disable interrupt */

	val = p->dma_read(IRQENABLE_L0, lch);

	val &= ~(1 << lch);

	p->dma_write(val, IRQENABLE_L0, lch);

	/* clear IRQ STATUS */

	p->dma_write(1 << lch, IRQSTATUS_L0, lch);

	spin_unlock_irqrestore(&dma_chan_lock, flags);

}
@@ -745,11 +754,8 @@ int omap_request_dma(int dev_id, const char *dev_name, 
	}



	if (cpu_class_is_omap2()) {

		omap2_enable_irq_lch(free_ch);

		omap_enable_channel_irq(free_ch);

		/* Clear the CSR register and IRQ status register */

		p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch);

		p->dma_write(1 << free_ch, IRQSTATUS_L0, 0);

		omap2_enable_irq_lch(free_ch);

	}



	*dma_ch_out = free_ch;
@@ -768,27 +774,19 @@ void omap_free_dma(int lch) 
		return;

	}



	if (cpu_class_is_omap1()) {

		/* Disable all DMA interrupts for the channel. */

		p->dma_write(0, CICR, lch);

		/* Make sure the DMA transfer is stopped. */

		p->dma_write(0, CCR, lch);

	}



	if (cpu_class_is_omap2()) {

	/* Disable interrupt for logical channel */

	if (cpu_class_is_omap2())

		omap2_disable_irq_lch(lch);



		/* Clear the CSR register and IRQ status register */

		p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);

		p->dma_write(1 << lch, IRQSTATUS_L0, lch);



	/* Disable all DMA interrupts for the channel. */

		p->dma_write(0, CICR, lch);

	omap_disable_channel_irq(lch);



	/* Make sure the DMA transfer is stopped. */

	p->dma_write(0, CCR, lch);



	/* Clear registers */

	if (cpu_class_is_omap2())

		omap_clear_dma(lch);

	}



	spin_lock_irqsave(&dma_chan_lock, flags);

	dma_chan[lch].dev_id = -1;
@@ -943,8 +941,7 @@ void omap_stop_dma(int lch) 
	u32 l;



	/* Disable all interrupts on the channel */

	if (cpu_class_is_omap1())

		p->dma_write(0, CICR, lch);

	omap_disable_channel_irq(lch);



	l = p->dma_read(CCR, lch);

	if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&