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Commit beab79b3 authored by Yan He's avatar Yan He
Browse files

msm: ep_pcie: support both PARF based MSI and iATU based MSI 



Add the support to generate both PCIe PARF based MSI generation
and iATU based address write MSI generation for unit test.

Change-Id: I8c5abf8dcae4ebf2c33fee182f6bc147979f74dd
Signed-off-by: default avatarYan He <yanhe@codeaurora.org>
parent 6ffca736

drivers/platform/msm/ep_pcie/ep_pcie_com.h

+1 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ 
#define PCIE20_PARF_TEST_BUS           0xE4

#define PCIE20_PARF_MHI_BASE_ADDR_LOWER 0x178

#define PCIE20_PARF_MHI_BASE_ADDR_UPPER 0x17c

#define PCIE20_PARF_MSI_GEN             0x188

#define PCIE20_PARF_DEBUG_INT_EN        0x190

#define PCIE20_PARF_MHI_IPA_DBS                0x198

#define PCIE20_PARF_MHI_IPA_CDB_TARGET_LOWER   0x19C

drivers/platform/msm/ep_pcie/ep_pcie_core.c

+27 −20
Original line number Diff line number Diff line
@@ -1832,16 +1832,22 @@ int ep_pcie_core_trigger_msi(u32 idx) 
			ep_pcie_dev.rev, ep_pcie_dev.msi_counter,

			data + idx, idx,

			ep_pcie_dev.active_config ? "" : "not");



		if (ep_pcie_dev.active_config) {

			u32 status;



			ep_pcie_write_reg(ep_pcie_dev.dm_core,

				PCIE20_MSI_MASK, idx);

			if (ep_pcie_dev.msi_counter % 2) {

				EP_PCIE_DBG2(&ep_pcie_dev,

					"PCIe V%d: try to trigger MSI by PARF_MSI_GEN.\n",

					ep_pcie_dev.rev);

				ep_pcie_write_reg(ep_pcie_dev.parf,

					PCIE20_PARF_MSI_GEN, idx);

				status = readl_relaxed(ep_pcie_dev.parf +

					PCIE20_PARF_LTR_MSI_EXIT_L1SS);

				while ((status & BIT(1)) && (max_poll-- > 0)) {

					udelay(MSI_EXIT_L1SS_WAIT);

				status = readl_relaxed(ep_pcie_dev.parf +

					status = readl_relaxed(ep_pcie_dev.parf

						+

						PCIE20_PARF_LTR_MSI_EXIT_L1SS);

				}

				if (max_poll == 0)
@@ -1852,12 +1858,13 @@ int ep_pcie_core_trigger_msi(u32 idx) 
					EP_PCIE_DBG2(&ep_pcie_dev,

						"PCIe V%d: MSI_EXIT_L1SS has been cleared.\n",

						ep_pcie_dev.rev);



			} else {

				EP_PCIE_DBG2(&ep_pcie_dev,

						"PCIe V%d: try to trigger MSI by direct address write as well.\n",

						ep_pcie_dev.rev);

			ep_pcie_write_reg(ep_pcie_dev.msi, addr & 0xfff, data

						+ idx);

				ep_pcie_write_reg(ep_pcie_dev.msi, addr & 0xfff,

							data + idx);

			}

		} else {

			ep_pcie_write_reg(ep_pcie_dev.msi, addr & 0xfff, data

						+ idx);