Loading drivers/clk/msm/clock-gcc-titanium.c +3 −3 Original line number Diff line number Diff line Loading @@ -97,7 +97,7 @@ DEFINE_CLK_RPM_SMD_XO_BUFFER(rf_clk2, rf_clk2_a, RF_CLK2_ID); DEFINE_CLK_RPM_SMD_XO_BUFFER(rf_clk3, rf_clk3_a, RF_CLK3_ID); DEFINE_CLK_RPM_SMD_XO_BUFFER(bb_clk1, bb_clk1_a, BB_CLK1_ID); DEFINE_CLK_RPM_SMD_XO_BUFFER(bb_clk2, bb_clk2_a, BB_CLK2_ID); DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk1, div_clk1_a, DIV_CLK1_ID); DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk2, div_clk2_a, DIV_CLK2_ID); DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(bb_clk1_pin, bb_clk1_a_pin, BB_CLK1_ID); DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(bb_clk2_pin, bb_clk2_a_pin, BB_CLK2_ID); Loading Loading @@ -3456,8 +3456,8 @@ static struct clk_lookup msm_clocks_lookup[] = { CLK_LIST(bb_clk2_a), CLK_LIST(bb_clk2_pin), CLK_LIST(bb_clk2_a_pin), CLK_LIST(div_clk1), CLK_LIST(div_clk1_a), CLK_LIST(div_clk2), CLK_LIST(div_clk2_a), CLK_LIST(gpll0_clk_src), CLK_LIST(gpll6_clk_src), CLK_LIST(gpll2_clk_src), Loading include/dt-bindings/clock/msm-clocks-hwio-titanium.h +1 −0 Original line number Diff line number Diff line Loading @@ -669,6 +669,7 @@ static DEFINE_VDD_REGS_INIT(vdd_gfx, 1); #define RF_CLK2_ID 0x5 #define RF_CLK3_ID 0x8 #define DIV_CLK1_ID 0xB #define DIV_CLK2_ID 0xC #endif include/dt-bindings/clock/msm-clocks-titanium.h +2 −2 Original line number Diff line number Diff line Loading @@ -285,8 +285,8 @@ #define clk_rf_clk2_a 0x944d8bbd #define clk_rf_clk3 0xb673936b #define clk_rf_clk3_a 0xf7975f21 #define clk_div_clk1 0xaa1157a6 #define clk_div_clk1_a 0x6b943d68 #define clk_div_clk2 0xd454019f #define clk_div_clk2_a 0x4bd7bfa8 /* clock_debug controlled clocks */ #define clk_gcc_debug_mux 0x8121ac15 Loading Loading
drivers/clk/msm/clock-gcc-titanium.c +3 −3 Original line number Diff line number Diff line Loading @@ -97,7 +97,7 @@ DEFINE_CLK_RPM_SMD_XO_BUFFER(rf_clk2, rf_clk2_a, RF_CLK2_ID); DEFINE_CLK_RPM_SMD_XO_BUFFER(rf_clk3, rf_clk3_a, RF_CLK3_ID); DEFINE_CLK_RPM_SMD_XO_BUFFER(bb_clk1, bb_clk1_a, BB_CLK1_ID); DEFINE_CLK_RPM_SMD_XO_BUFFER(bb_clk2, bb_clk2_a, BB_CLK2_ID); DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk1, div_clk1_a, DIV_CLK1_ID); DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk2, div_clk2_a, DIV_CLK2_ID); DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(bb_clk1_pin, bb_clk1_a_pin, BB_CLK1_ID); DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(bb_clk2_pin, bb_clk2_a_pin, BB_CLK2_ID); Loading Loading @@ -3456,8 +3456,8 @@ static struct clk_lookup msm_clocks_lookup[] = { CLK_LIST(bb_clk2_a), CLK_LIST(bb_clk2_pin), CLK_LIST(bb_clk2_a_pin), CLK_LIST(div_clk1), CLK_LIST(div_clk1_a), CLK_LIST(div_clk2), CLK_LIST(div_clk2_a), CLK_LIST(gpll0_clk_src), CLK_LIST(gpll6_clk_src), CLK_LIST(gpll2_clk_src), Loading
include/dt-bindings/clock/msm-clocks-hwio-titanium.h +1 −0 Original line number Diff line number Diff line Loading @@ -669,6 +669,7 @@ static DEFINE_VDD_REGS_INIT(vdd_gfx, 1); #define RF_CLK2_ID 0x5 #define RF_CLK3_ID 0x8 #define DIV_CLK1_ID 0xB #define DIV_CLK2_ID 0xC #endif
include/dt-bindings/clock/msm-clocks-titanium.h +2 −2 Original line number Diff line number Diff line Loading @@ -285,8 +285,8 @@ #define clk_rf_clk2_a 0x944d8bbd #define clk_rf_clk3 0xb673936b #define clk_rf_clk3_a 0xf7975f21 #define clk_div_clk1 0xaa1157a6 #define clk_div_clk1_a 0x6b943d68 #define clk_div_clk2 0xd454019f #define clk_div_clk2_a 0x4bd7bfa8 /* clock_debug controlled clocks */ #define clk_gcc_debug_mux 0x8121ac15 Loading